IPT-DSPBUILDER Altera, IPT-DSPBUILDER Datasheet - Page 41

• Manufacturer Part Number: IPT-DSPBUILDER
• Description: DSP BUILDER SOFTWARE
• Manufacturer: Altera
• Type: DSPr

Specifications of IPT-DSPBUILDER

• Function: DSP Builder
• License: Initial License
• Software Application: IP CORE, DSP BUILDER
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Supported Families: Arria GX, Arria II GX, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: Not applicable / Not applicable

Chapter 2: Getting Started
Performing RTL Simulation
© June 2010 Altera Corporation
5. Click the Advanced tab
Figure 2–12. Testbench Generator Dialog Box Advanced Tab
6. Turn on the Launch GUI option. This option causes the ModelSim GUI to launch
7. Click Generate HDL to generate a VDHL-based testbench from your model.
8. Click Run Simulink to generate Simulink simulation results for the testbench.
9. Click Run ModelSim to load your design into ModelSim.
10. All waveforms initially show using digital format in the ModelSim Wave window.
when you invoke the ModelSim simulation.
Your design simulates with the output displaying in the ModelSim Wave window.
The testbench initializes all your design registers with a pulse on the aclr input
signal.
Change the format of the sinin, sindelay and streammod signals to analog.
1
In ModelSim 6.4a, you can right-click to display the popup menu, point to
Format and click on Analog (Automatic). The user interface commands
may be different in other versions of ModelSim.
(Figure
Preliminary
2–12).
DSP Builder Standard Blockset User Guide
2–19