IPT-DSPBUILDER Altera, IPT-DSPBUILDER Datasheet - Page 241

• Manufacturer Part Number: IPT-DSPBUILDER
• Description: DSP BUILDER SOFTWARE
• Manufacturer: Altera
• Type: DSPr

Specifications of IPT-DSPBUILDER

• Function: DSP Builder
• License: Initial License
• Software Application: IP CORE, DSP BUILDER
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Supported Families: Arria GX, Arria II GX, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: Not applicable / Not applicable

Chapter 2: Arithmetic Library
SOP Tap
Table 2–49. Product Block I/O Formats (Part 2 of 2)
Figure 2–19. Product Block Example
SOP Tap
© June 2010 Altera Corporation
I/O
O
Notes to
(1) For signed integers and signed binary fractional numbers, the MSB is the sign bit.
(2) [L] is the number of bits on the left side of the binary point; [R] is the number of bits on the right side of the binary point. For signed or unsigned
(3) I1
(4) Explicit means that the port bit width information is a block parameter. Implicit means that the port bit width information is set by the datapath
integers R = 0, that is, [L].[0]. For single bits, R = 0, that is, [1] is a single bit.
bit width propagation mechanism. To specify the bus format of an implicit input port, use a Bus Conversion block to set the width.
O1
R2)]
[L].[R]
Simulink (2),
[2×max(L1,L2].[2×max(R1,
Table
is an input port. O1
f
2–49:
(3)
Figure 2–19
For more information about multiplier operations, refer to the
User
The SOP Tap block performs a sum of products for two or four taps. Use this block to
build two or four tap FIR filters, or cascade blocks to create filters with more taps.
The SOP Tap block implements with a multiplier-adder, which has registers on the
inputs, multipliers and adders. Thus, the result always lags the input by 3 cycles. The
dout port is assigned the value of din(n-t) where t is the number of taps. The block
has the following equations:
For 2 taps:
For 4 taps:
Table 2–50
[L].[R]
q(n+3) = c
dout(n+2) = din(n)
q(n+3) = c
dout(n+4) = din(n)
Guide.
O1: out STD_LOGIC_VECTOR({2×max(L1,L2) + 2×max(R1,R2) - 1} DOWNTO 0) Implicit
is an output port.
shows the SOP Tap block inputs and outputs.
shows an example with the Product block.
0
0
(n)×din(n) + c
(n)×din(n) + c
(Note 1)
1
1
(n)×din(n-1)
(n)×din(n-1) + c
Preliminary
VHDL
2
(n)×din(n-2) + c
DSP Builder Standard Blockset Libraries
3
(n)×din(n-3)
lpm_mult Megafunction
Type
(4)
2–33