IPT-DSPBUILDER Altera, IPT-DSPBUILDER Datasheet - Page 418

• Manufacturer Part Number: IPT-DSPBUILDER
• Description: DSP BUILDER SOFTWARE
• Manufacturer: Altera
• Type: DSPr

Specifications of IPT-DSPBUILDER

• Function: DSP Builder
• License: Initial License
• Software Application: IP CORE, DSP BUILDER
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Supported Families: Arria GX, Arria II GX, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: Not applicable / Not applicable

Index–4
ModelSim
Multiple Port External RAM block
Multiplexer block
Multiplier block
Multiply Accumulate block
Multiply Add block
Multi-Rate DFF block
N
Naming conventions
Nios II
Non-synthesizable Input block
Non-synthesizable Output block
Notation
O
Output block
P
Packet Format Converter
Parallel Adder Subtractor
Parallel To Serial block
Pattern block
Pipeline depth
Pipelined Adder block
PLL block
PLL clocks
Port data type
Product block
Q
Quartus II assignments
Quartus II constraints
Quartus II project
Quartus II Project Global Assignment block
DSP Builder Handbook Volume 2: DSP Builder Standard Blockset
Creating
Performing RTL simulation
Simulating in Simulink
Comparison with Simulink
Simulation fllow
Using a Tcl file to add commands
Support
Using the Nios II IDE
Binary point location
Fixed-point
Avalon-ST
display
device support
display format
Adding to block entity names
Adding to a model
Adding a DSP Builder design
Integration of multiple models
7–3
3–24
1–2
2–4
6–17
4–22
2–31
7–22
3–2
2–21
4–20
3–24
3–14
2–25
3–19
3–1
7–1
2–29
9–14
3–23
3–3
7–15
2–27
2–15
2–23
6–15
3–22
2–17
6–16
2–20
3–27
8–3
12–5
3–27
1–11
Preliminary
Quartus II Project Pinout Assignments block
R
Rate Change library
Real-Imag to Complex block
Release information
Reset
Resource usage
Resource Usage block
ROM block
Round block
S
Saturate block
Serial To Parallel block
Shift Taps block
Signal Compiler
Signal Compiler block
Signal data type
SignalTap II
SignalTap II logic analyzer
SignalTap II Logic Analyzer block
SignalTap II Node block
Simulation
Simulation flow
Simulation library
Simulation model
Simulink
Single Pulse block
Single-Port RAM block
Solver
Asynchronous
global
Analyzing
Adding to a model
Enabling SignalTap II options
License
Synthesis and compilation flows
display format
Design flow
Walkthrough
Features
Performing logic analysis
Signal Compiler options
Trigger conditions
Setting the Simulink solver
Using ModelSim
Using Simulink
HDL
Comparison with ModelSim
Integration with
Solver
Setting simulation parameters
3–16
3–17
3–16
9–16
13–1
1–2
6–18
6–20
3–25
9–20
3–19
3–19
6–1
6–2
4–23
8–1
3–17
3–24
2–15
7–1
1–1
1–3
2–17
1–12
1–13
6–7
9–18
2–16
9–21
1–15
© June 2010 Altera Corporation
6–1
6–6
3–14
6–1
2–3
3–22
6–6
1–14
2–3
3–19
1–11