IPT-DSPBUILDER Altera, IPT-DSPBUILDER Datasheet - Page 138

• Manufacturer Part Number: IPT-DSPBUILDER
• Description: DSP BUILDER SOFTWARE
• Manufacturer: Altera
• Type: DSPr

Specifications of IPT-DSPBUILDER

• Function: DSP Builder
• License: Initial License
• Software Application: IP CORE, DSP BUILDER
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Supported Families: Arria GX, Arria II GX, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: Not applicable / Not applicable

8–8
Figure 8–7. Library: filter8tap/fir_vhdl Window
Building the Black-Box SubSystem Simulation Model
DSP Builder Standard Blockset User Guide
8. Double-click on the fir_vhdl symbol. The filter8tap/fir_vhdl subsystem opens
9. Leave your model window open for use in the next section.
For this example, you use a S-function C++ simulation model to represent the 8-tap
FIR filter block. To create your model, follow these steps:
1. In the Simulink Library Browser, expand the Simulink folder.
2. From the User-Defined Functions library, drag and drop a S-Function block
3. Double-click the S-Function block to display the Function Block Parameters:
4. In the Block Parameters dialog box, change the S-Function name to Sfir8tap
5. Click the Edit button to view the code that describes the S-Function.
(Figure
The subsystem contains two HDL Input blocks (simulink_sclr and
data_in) and a HDL Output block (data_out). Each of these blocks in turn
connects to a subsystem input or output. DSP Builder also creates a HDL Entity
block to store the name of the HDL file and the names of the clock and reset ports.
1
In the next section, you build the simulation model that represents the
functionality of this block in your Simulink simulations.
into your model window.
S-Function dialog box.
and enter the parameters -1 3962 4817 5420 5733 5733 5420 4817 3962.
The Sfir8tap function is a C++ Simulink S-Function simulation model for the
8-tap Fir filter block.
The first parameter refers to the sampling rate (-1 indicates it inherits the sampling
rate from the preceding block) and the rest of the parameters represent the eight
filter coefficients.
1
The clock is handled implicitly and no port is explicitly created in the
subsystem.
Leave the S-function modules parameter with its default value.
8–7).
Preliminary
Chapter 8: Using Black Boxes for HDL Subsystems
Subsystem Builder Design Example
© June 2010 Altera Corporation