IPT-DSPBUILDER Altera, IPT-DSPBUILDER Datasheet - Page 370

• Manufacturer Part Number: IPT-DSPBUILDER
• Description: DSP BUILDER SOFTWARE
• Manufacturer: Altera
• Type: DSPr

Specifications of IPT-DSPBUILDER

• Function: DSP Builder
• License: Initial License
• Software Application: IP CORE, DSP BUILDER
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Supported Families: Arria GX, Arria II GX, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: Not applicable / Not applicable

10–2
Table 10–1. State Machine Wizard Parameters
DSP Builder Standard Blockset Libraries
States
Input ports
State transitions
Transition to source
state if not specified
Output ports
Action conditions
Name
f
user specified
user specified
user specified
user specified
On, Off
user specified
Use Verilog HDL syntax to specify the conditional statements that you specify for
state transitions and output actions.
define a conditional expression.
Table 10–2. State Machine Editor Operators
A conditional statement consists of a source state, a condition that causes a transition
to take place, and the destination state to which the state machine transitions. The
source state and destination state values must be valid state names, which you can
select from a drop down list in the wizard.
The state machine description is saved in a <block name>.smf file when you close the
state machine wizard.
The syntax of each conditional statement is automatically checked on entry and the
completed state machine is validated when you generate HDL to ensure that the state
machine is functionally correct.
For more information including procedures for drawing a graphical state machine,
refer to the About the State Machine Editor topic in the Quartus II Help.
When you exit from the State Machine Editor, the generated HDL is compiled in the
Quartus II software and the ports updated on the block in your Simulink model.
Figure 10–2
Editor wizard creates and includes in a simple Simulink model.
~ (unary)
(...)
==
!=
>
>=
<
<=
&
|
Operator
Value
shows an example of the default state machine that the State Machine
You can specify any number of input port names that must be valid HDL identifiers.
Turn on to always transition to the source state if not all transition conditions are
You can specify any number of output port names that must be valid HDL
You can specify any number of state names that must be valid HDL identifiers.
You can specify any number of conditional statements for the transitions between
source and destination states.
specified.
identifiers.
You can specify actions assigned to each output port.
Negative
Brackets
Numeric equality
Not equal to
Greater than
Greater than or equal to
Less than
Less than or equal to
AND
OR
Description
Preliminary
Table 10–2
1
1
2
2
2
2
2
2
2
2
Description
Priority
shows the operators you can use to
Chapter 10: State Machine Functions Library
~in1
(1)
in1==5
in1!=5
in1>in2
in1>=in2
in1<in2
in1<=in2
(in1==in2)&(in3>=4)
(in1==in2)|(in1>in2)
© June 2010 Altera Corporation
Example
State Machine Editor