IPT-DSPBUILDER Altera, IPT-DSPBUILDER Datasheet - Page 333

• Manufacturer Part Number: IPT-DSPBUILDER
• Description: DSP BUILDER SOFTWARE
• Manufacturer: Altera
• Type: DSPr

Specifications of IPT-DSPBUILDER

• Function: DSP Builder
• License: Initial License
• Software Application: IP CORE, DSP BUILDER
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Supported Families: Arria GX, Arria II GX, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: Not applicable / Not applicable

Chapter 7: Rate Change Library
PLL
PLL
Table 7–4. PLL Block Parameters (Part 1 of 2)
© June 2010 Altera Corporation
Input Clock:
Use Base Clock
Number of Output Clocks 1–9
Output Clocks
Period Multiplier
Period Divider
Name
f
1
The PLL block generates a clock signal that is based on a reference clock.
Phase-locked loops (PLL) have become an important building block of most
high-speed digital systems today. Their use ranges from improving timing as zero
delay lines to full-system clock synthesis. The Arria, Cyclone, and Stratix series device
families offer advanced on-chip PLL features that were previously offered only by the
most complex discrete devices.
Each PLL has multiple outputs that can source any of the 40 system clocks in the
devices to give you complete control over your clocking needs. The PLLs offer full
frequency synthesis capability (the ability to multiply up or divide down the clock
period) and phase shifting for optimizing I/O timing. Additionally, the PLLs have
high-end features such as programmable bandwidth, spread spectrum, and clock
switchover.
The PLL block generates internal clocks with frequencies that are multiples of the
frequency of the system clock. PLLs on the FPGA can simultaneously multiply and
divide the reference clock. The PLL block checks the validity of the parameters.
If you use a PLL block to define clock signals when there is no Clock block in your
design, the PLL-derived clocks might not pass the derived period correctly to the
blocks referencing the PLL-derived clock. Always explicitly include a Clock block
with a PLL block.
The number of PLL internal clock outputs supported by each device family depends
on the specific device packaging.
For information about the built-in PLLs, refer to the device handbook for the device
family you target.
The following restrictions apply when you use a PLL block:
■
■
Table 7–4
Your design may contain more than one PLL block but they must be at the top
level.
Each output clock of the PLL has a zero degree phase shift and 50% duty cycle.
User specified
On or Off
<PLL block name>_clk0 to
<PLL block name>_clk8
(1)
(1)
shows the PLL block parameters.
Value
Specify the name of the input clock signal.
Turn on to use the base clock.
The number of PLL clock outputs.
Select the PLL clock that you want to set frequency multiplier and
divider factors for.
Multiply the reference clock period by this value.
Divide the reference clock period by this value.
Preliminary
Description
DSP Builder Standard Blockset Libraries
7–3