IPT-DSPBUILDER Altera, IPT-DSPBUILDER Datasheet - Page 305

• Manufacturer Part Number: IPT-DSPBUILDER
• Description: DSP BUILDER SOFTWARE
• Manufacturer: Altera
• Type: DSPr

Specifications of IPT-DSPBUILDER

• Function: DSP Builder
• License: Initial License
• Software Application: IP CORE, DSP BUILDER
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Supported Families: Arria GX, Arria II GX, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: Not applicable / Not applicable

Chapter 5: Interfaces Library
Avalon-ST Sink
Table 5–13. Signals Supported by the Avalon-ST Sink Block
Table 5–14. Avalon-ST Sink Block Parameters
© June 2010 Altera Corporation
DataIn
Valid
Ready
startofpacket Input
endofpacket
empty
Specify Clock
Clock
Data Type
[number of bits].[] >= 0
[].[number of bits] >= 0
Symbol Width
Use endofpacket
Use startofpacket
Use empty
Ready Latency
Name
Signal
f
On or Off
User defined
Signed Integer,
Signed Fractional,
Unsigned Integer
(Parameterizable)
(Parameterizable)
>= 1
On or Off
On or Off
On or Off
0 or 1
Direction
Input
Input
Output
Input
Input
For information about the Avalon-ST interface, refer to the
Specifications.
Table 5–13
Table 5–14
Value
Data input bus.
Data valid signal that indicates the validity of the input data signals.
Data input ready signal. Indicates that the sink can accept data.
This signal is available when Use startofpacket is on and marks the active cycle
containing the start of the packet.
This signal is available when Use endofpacket is on and marks the active cycle
containing the end of the packet.
This signal is available when Use empty is turned on and the bit width is greater than the
symbol width. It specifies how many of the symbols in a packet are empty. For example,
a 32-bit wide bus with 8-bit symbols can have an empty value from 0 to 3.
lists the signals supported by the Avalon-ST Sink block.
shows the Avalon-ST Sink block parameters.
Turn on to explicitly specify the clock name.
Specifies the clock signal name.
The number format of the bus.
Specifies the number of bits to the left of the binary point, including the sign bit.
Read and write buses must have the same number of bits.
Specifies the number of bits to the right of the binary point. This parameter applies
only to signed fractional buses.
Specifies the symbol width in bits.
When this option is on, the endofpacket port is available on the Avalon-ST
Sink block.
When this option is on, the startofpacket port is available on the
Avalon-ST Sink block.
empty port is available on the Avalon-ST Sink block.
Defines the relationship between assertion or deassertion of the Ready signal and
cycles the ones ready for data transfer separately for each interface.
When this option is on and the bit width is greater than the symbol width, the
Preliminary
Description
Description
DSP Builder Standard Blockset Libraries
Avalon Interface
5–19