IPT-DSPBUILDER Altera, IPT-DSPBUILDER Datasheet - Page 297

• Manufacturer Part Number: IPT-DSPBUILDER
• Description: DSP BUILDER SOFTWARE
• Manufacturer: Altera
• Type: DSPr

Specifications of IPT-DSPBUILDER

• Function: DSP Builder
• License: Initial License
• Software Application: IP CORE, DSP BUILDER
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Supported Families: Arria GX, Arria II GX, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: Not applicable / Not applicable

Chapter 5: Interfaces Library
Avalon-MM Write FIFO
Avalon-MM Write FIFO
Table 5–7. Signals Supported by the Avalon-MM Write FIFO Block
Table 5–8. Avalon-MM Write FIFO Block Parameters
© June 2010 Altera Corporation
TestData
Stall
Ready
DataOut
DataValid Output
Data Type
[number of bits].[] >= 0
[].[number of bits] >= 0
FIFO Depth
Signal
Name
f
Input
Input
Input
Output
Direction
Signed Integer,
Signed Fractional,
Unsigned Integer
(Parameterizable)
(Parameterizable)
> 2
The Avalon-MM Write FIFO block is essentially an Avalon-MM Slave block
configured to implement a write FIFO.
For information about the Avalon-MM Slave block, refer to
page
Table 5–7
Table 5–8
Figure 5–8
Figure 5–8. Avalon-MM Write FIFO
Value
This port must be connected to Simulink blocks. It provides simulation data to the Avalon-MM
write FIFO. The data is passed to the DataOut port one cycle after the Ready input port is
asserted.
This port must be connected to Simulink blocks. It simulates stall conditions of the Avalon-MM
bus and hence underflow to the SOPC component. For any simulation cycle where Stall is
asserted, the test data is cached by the Avalon-MM write converter and released in order, one
sample per clock, when stall is de-asserted.
This port must be connected to DSP Builder blocks. It indicates that the downstream hardware
is ready for data.
This port should be connected to DSP Builder blocks and corresponds to the oldest unsent
data sample received on the TestData port.
This port should be connected to DSP Builder blocks and is asserted whenever DataOut
corresponds to real data.
5–6.
lists the signals supported by the Avalon-MM Write FIFO block.
shows the Avalon-MM Write FIFO block parameters.
shows an Avalon-MM Write FIFO block.
The number format of the bus.
Specifies the number of bits to the left of the binary point, including the sign bit.
This parameter does not apply to single-bit buses.
Specifies the number of bits to the right of the binary point. This parameter applies
only to signed fractional buses.
Specifies the depth of the FIFO buffer.
Preliminary
Description
Description
DSP Builder Standard Blockset Libraries
“Avalon-MM Slave” on
5–11