IPT-DSPBUILDER Altera, IPT-DSPBUILDER Datasheet - Page 245

• Manufacturer Part Number: IPT-DSPBUILDER
• Description: DSP BUILDER SOFTWARE
• Manufacturer: Altera
• Type: DSPr

Specifications of IPT-DSPBUILDER

• Function: DSP Builder
• License: Initial License
• Software Application: IP CORE, DSP BUILDER
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Supported Families: Arria GX, Arria II GX, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: Not applicable / Not applicable

Chapter 2: Arithmetic Library
Sum of Products
Table 2–57. Sum of Products Block Parameters
© June 2010 Altera Corporation
Input Data Number of
Bits
Number of
Coefficients
Coefficients Number
of Bits
Signed Integer
Fixed-Coefficient
Values
Number of Pipeline
Stages
Full Resolution for
Output Result
Output Number of Bits >= 0
Output Truncated LSB
FPGA Implementation
Use Enable Port
Use Asynchronous
Clear Port
Name
Table 2–56. Sum of Products Block Inputs and Outputs
Table 2–57
Table 2–58
a(0) to a(n–1) Input
ena
aclr
q
>= 0
(Parameterizable)
1–8
>= 1
(Parameterizable)
Vector
(Parameterizable)
>= 0
(Parameterizable)
On or Off
(Parameterizable)
>= 0
(Parameterizable)
Distributed Arithmetic,
Dedicated Multiplier
Circuitry, Auto
On or Off
On or Off
Signal
Value
lists the parameters for the Sum of Products block.
shows the Sum of Product block I/O formats.
Direction
Input
Input
Output
Specify the number of bits to the left of the binary point of all input
signals.
The number of coefficients.
Specify the number of bits to the left of the binary point of all non-variable
coefficients represented as a signed integer.
Specify the coefficient values for each port as a sequence of signed
integers.
For example: [-587 -844 -678 -100 367 362 71 -244]
Specify the number of pipeline stages.
When on, the multiplier output bit width is full resolution. When off, you
can specify the number of bits in the output signal and the number of
least significant bits (LSBs) truncated from the output signal.
Specify the number of bits in the output signal.
Specify the number of LSBs to be truncated from the output signal.
Use a distributed arithmetic, dedicated multiplier or automatically
determined implementation.
Turn on to use the clock enable input (ena).
Turn on to use the asynchronous clear input (aclr).
Preliminary
1 to 8 ports corresponding to the signed integer fixed coefficient
values specified in the block parameters.
Optional clock enable.
Optional asynchronous clear.
Result.
Description
Description
DSP Builder Standard Blockset Libraries
2–37