IPT-DSPBUILDER Altera, IPT-DSPBUILDER Datasheet - Page 334

• Manufacturer Part Number: IPT-DSPBUILDER
• Description: DSP BUILDER SOFTWARE
• Manufacturer: Altera
• Type: DSPr

Specifications of IPT-DSPBUILDER

• Function: DSP Builder
• License: Initial License
• Software Application: IP CORE, DSP BUILDER
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Supported Families: Arria GX, Arria II GX, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: Not applicable / Not applicable

7–4
Table 7–4. PLL Block Parameters (Part 2 of 2)
Tsamp
Table 7–6. Tsamp Block Parameters
Table 7–7. Tsamp Block I/O Formats
DSP Builder Standard Blockset Libraries
Export As Output Pin
Note to
(1) Refer to the device documentation for the device family you target.
Specify Clock
Clock Name
I
O
Notes to
(1) For signed integers and signed binary fractional numbers, the MSB is the sign bit.
(2) [L] is the number of bits on the left side of the binary point; [R] is the number of bits on the right side of the binary point. For signed or unsigned
(3) I1
(4) Explicit means that the port bit width information is a block parameter. Implicit means that the port bit width information is set by the datapath
I/O
integers R = 0, that is, [L].[0]. For single bits, R = 0, that is, [1] is a single bit.
bit width propagation mechanism. To specify the bus format of an implicit input port, use a Bus Conversion block to set the width.
I1
O1
[L].[R]
Table
[L].[R]
Name
[L].[R]
Table
Simulink (2),
Name
is an input port. O1
7–4:
7–7:
1
The Tsamp block sets the clock domain inherited by all downstream blocks.
When you use the Tsamp block, you must select a variable step solver in the Simulink
configuration parameters. Unless the downstream clock is an exact, slower multiple
of the upstream clock, the simulation results may not match ModelSim; in this case it
is better to use a
Table 7–5
Table 7–5. Tsamp Block Inputs and Outputs
Table 7–6
Table 7–7
Figure 7–2 on page 7–5
(3)
<unnamed>
<unnamed>
On or Off
User specified
[L].[R]
On or Off
Value
Signal
is an output port.
I1: in STD_LOGIC_VECTOR({L + R - 1} DOWNTO 0)
O1: out STD_LOGIC_VECTOR({L + R - 1} DOWNTO 0)
shows the Tsamp block inputs and outputs.
shows the Tsamp block parameters.
shows the Tsamp block I/O formats.
Value
(Note 1)
Turn on to explicitly specify the clock name.
Specify the name of the
Multi-Rate DFF
Input
Output
Direction
shows an design example with the Tsamp block.
Turn on to export this clock as an output pin.
Preliminary
Input data port.
Output data port.
block.
Clock
VHDL
block that specifies the clock signal.
Description
Description
Description
© June 2010 Altera Corporation
Chapter 7: Rate Change Library
Type
Implicit
Implicit
Tsamp
(4)