IPT-DSPBUILDER Altera, IPT-DSPBUILDER Datasheet - Page 403

• Manufacturer Part Number: IPT-DSPBUILDER
• Description: DSP BUILDER SOFTWARE
• Manufacturer: Altera
• Type: DSPr

Specifications of IPT-DSPBUILDER

• Function: DSP Builder
• License: Initial License
• Software Application: IP CORE, DSP BUILDER
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Supported Families: Arria GX, Arria II GX, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: Not applicable / Not applicable

Chapter 13: Design Examples
MAC based 32 Tap FIR Filter
MAC based 32 Tap FIR Filter
Color Space Converter
Farrow Based Resampler
© June 2010 Altera Corporation
The example model is AltrFir32.mdl.
This design example illustrates how to implement a MAC-based, fixed-coefficient,
32-tap, low pass FIR (finite impulse response) filter with a single
Accumulate
requires the MathWorks Signal Processing ToolBox to calculate the coefficient with the
fir1 function:
The example model is FIR_MAC32.mdl.
This design example illustrates how to implement a color space converter, which
converts R'G'B to Y'C'bCr.
The example model is TopCsc.mdl.
This design example illustrates how to implement a Farrow based decimating sample
rate converter.
Many integrated systems, such as software defined radios (SDR), require you to
resample data so that a unit can comply with communication standards where the
sample rates are different. In some cases, where one clock rate is a simple integer
multiple of another clock rate, use interpolating and decimating FIR filters to
accomplish resampling. However, in most cases the interpolation and decimation
factors are so high that this approach is impractical.
Farrow resamplers provide an efficient way to resample a data stream at a different
sample rate. The underlying principle is that the phase difference between the current
input and wanted output is determined on a sample by sample basis. This phase
difference then combines the phases of a polyphase filter in such a way that a sample
for the output phase, which you want, generates.
plot(FpCoef,'o');
title('Fixed-point scaled coefficient value');
ImpulseData = zeros(1,1000);
ImpulseData(1) = 100;
h = conv(ImpulseData,FpCoef);
fftplot(h);
title('FIR Frequency response');
FirSamplingPeriod=1;
coef = fix(fir1(32,3/8)*2^16-1);
Impulse =
Impulse(1) = 1;
h = conv(coef,Impulse);
plot(coef,'o');
title('Fixed-point scaled coefficient value');
fftplot(h);
title('Impulse Frequency response');
block and a single memory element for the tap delay line. This design
zeros(1,1000);
Preliminary
DSP Builder Standard Blockset Libraries
Multiply
13–7