IPT-DSPBUILDER Altera, IPT-DSPBUILDER Datasheet - Page 194

• Manufacturer Part Number: IPT-DSPBUILDER
• Description: DSP BUILDER SOFTWARE
• Manufacturer: Altera
• Type: DSPr

Specifications of IPT-DSPBUILDER

• Function: DSP Builder
• License: Initial License
• Software Application: IP CORE, DSP BUILDER
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Supported Families: Arria GX, Arria II GX, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: Not applicable / Not applicable

1–4
Table 1–3. Clock_Derived Block Parameters
Display Pipeline Depth
HDL Entity
Table 1–4. HDL Entity Block Parameters
DSP Builder Standard Blockset Libraries
Base Clock Multiplicand
Numerator
Base Clock Multiplicand
Denominator
Reset Name
Reset Type
Export As Output Pin
HDL File Name
Clock Name
Reset Name
HDL takes port names
from Subsystem
Name
Name
The Display Pipeline Depth block controls whether the pipeline depth displays
on primitive blocks.
You can change the display mode by double-clicking on the block. When set, the
current pipeline depth displays at the top right corner of each block that adds latency
to your design. The currently selected mode shows on the Display Pipeline
Depth block symbol.
Changing modes causes a Simulink display update, which may be slow for very large
designs.
The Display Pipeline Depth block has no parameters.
Use the HDL Entity block for black-box simulation subsystems that you include in
your design with a
name of the HDL file that DSP Builder substitutes for the subsystem and the names of
the clock and reset ports for the subsystem.
The
Table 1–4
User defined Specifies the name of the reset signal that the black-box subsystem uses.
User defined Specifies the name of the HDL file that DSP Builder substitutes for the subsystem
User defined Specifies the name of the clock signal that the black-box subsystem uses.
On or Off
>= 1
>= 1
User defined
Active Low,
Active High,
Synchronized
Active Low,
Synchronized
Active High
On or Off
Value
Subsystem Builder
Value
shows the parameters for the HDL Entity block.
represented by a Subsystem Builder block.
Turn on to use the subsystem port names as the entity port names instead of the
names of the HDL Input and HDL Output blocks.
Multiply the base clock period by this value. The resulting clock period should
be greater than 1ps but less than 2.1ms.
Divide the base clock period by this value. The resulting clock period should be
greater than 1ps but less than 2.1ms.
Specify a unique reset name. The default reset is aclr.
Specify whether the reset signal is active high or active low.
Turn on to export this clock as an output pin.
Subsystem Builder
block usually creates this block.
Preliminary
block. The HDL Entity block specifies the
Description
Description
© June 2010 Altera Corporation
Chapter 1: AltLab Library
Display Pipeline Depth