HD64F7047FW40V Renesas Electronics America, HD64F7047FW40V Datasheet - Page 108

• Manufacturer Part Number: HD64F7047FW40V
• Description: MCU 5V 256K I-TEMP,PB-FREE 100-Q
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7047r

Specifications of HD64F7047FW40V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 40MHz
• Connectivity: CAN, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

5.4.2
The interrupt priority is predetermined. When multiple interrupts occur simultaneously
(overlapped interruptions), the interrupt controller (INTC) determines their relative priorities and
starts the exception processing according to the results.
The priority of interrupts is expressed as priority levels 0 to 16, with priority 0 the lowest and
priority 16 the highest. The NMI interrupt has priority 16 and cannot be masked, so it is always
accepted. The priority level of user break interrupt and H-UDI is 15. IRQ interrupts and on-chip
peripheral module interrupt priority levels can be set freely using the INTC’s interrupt priority
level setting registers A, D to I, and K (IPRA, IPRD to IPRI, and IPRK) as shown in table 5.8. The
priority levels that can be set are 0 to 15. Level 16 cannot be set. See section 6.3.4, Interrupt
Priority Registers A, D to I, K (IPRA, IPRD to IPRI, IPRK), for more information on IPRA to
IPRK.
Table 5.8
5.4.3
When an interrupt occurs, the interrupt controller (INTC) ascertains its priority level. NMI is
always accepted, but other interrupts are only accepted if they have a priority level higher than the
priority level set in the interrupt mask bits (I3 to I0) of the status register (SR).
When an interrupt is accepted, exception processing begins. In interrupt exception processing, the
CPU saves SR and the program counter (PC) to the stack. The priority level value of the accepted
interrupt is written to SR bits I3 to I0. For NMI, however, the priority level is 16, but the value set
in I3 to I0 is H'F (level 15). Next, the start address of the exception service routine is fetched from
the exception processing vector table for the accepted interrupt, that address is jumped to and
execution begins. See section 6.6, Interrupt Operation, for more information on the interrupt
exception processing.
Rev. 2.00, 09/04, page 66 of 720
Type
NMI
User break
H-UDI
IRQ
On-chip peripheral module
Interrupt Priority Level
Interrupt Exception Processing
Interrupt Priority
Priority Level
16
15
15
0 to 15
Comment
Fixed priority level. Cannot be masked.
Fixed priority level.
A through K (IPRA to IPRK).
Fixed priority level.
Set with interrupt priority level setting registers