HD64F7047FW40V Renesas Electronics America, HD64F7047FW40V Datasheet - Page 530
HD64F7047FW40V
Manufacturer Part Number
HD64F7047FW40V
Description
MCU 5V 256K I-TEMP,PB-FREE 100-Q
Manufacturer
Renesas Electronics America
Series
SuperH® SH7047r
Datasheet
1.HD64F7047F50V.pdf
(766 pages)
Specifications of HD64F7047FW40V
Core Processor
SH-2
Core Size
32-Bit
Speed
40MHz
Connectivity
CAN, SCI
Peripherals
POR, PWM, WDT
Number Of I /o
53
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
12K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 16x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-QFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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16.3.2
The timer control register (TCNR) controls the enabling or disabling of interrupt requests, selects
the enabling or disabling of register access, and selects counter operation or halting.
Bit
7
6
5
4 to 2 —
1
0
Rev. 2.00, 09/04, page 488 of 720
Bit Name
TTGE
CST
RPRO
TGIEN
TGIEM
Timer Control Register (TCNR)
Initial
Value
0
0
0
All 0
0
0
R/W
R/W
R/W
R/W
R
R/W
R/W
Description
A/D Start-Conversion request Enable
Enables or disables the generation of A/D start-conversion
requests when the TGFN or TGFM bit of the timer status
register (TSR) is set.
0: Disable request
1: Enable request
Timer Counter Start
Selects operation or halting of the timer counter (TCNT)
and timer dead time counter (TDCNT).
0: TCNT and TDCNT operation is halted
1: TCNT and TDCNT perform count operations
Register Protects
Enables or disables the reading of registers other than
TSR, and enables or disables the writing to registers other
than TBRU to TBRW, TPBR, and TSR. Writes to TCNR
itself are also disabled. Note that reset input is necessary
in order to write to these registers again.
0: Register access enabled
1: Register access disabled
Reserved
These bits are always read as 0. Only 0 should be written
to these bits.
TGR Interrupt Enable N
Enables or disables interrupt requests by the TGFN bit
when TGFN is set to 1 in the TSR register.
0: Interrupt requests by TGFN bit disabled
1: Interrupt requests by TGFN bit enabled
TGR Interrupt Enable M
Enables or disables interrupt requests by the TGFM bit
when TGFM is set to 1 in the TSR register.
0: Interrupt requests by TGFM bit disabled
1: Interrupt requests by TGFM bit enabled
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