HD64F7047FW40V Renesas Electronics America, HD64F7047FW40V Datasheet - Page 605
HD64F7047FW40V
Manufacturer Part Number
HD64F7047FW40V
Description
MCU 5V 256K I-TEMP,PB-FREE 100-Q
Manufacturer
Renesas Electronics America
Series
SuperH® SH7047r
Datasheet
1.HD64F7047F50V.pdf
(766 pages)
Specifications of HD64F7047FW40V
Core Processor
SH-2
Core Size
32-Bit
Speed
40MHz
Connectivity
CAN, SCI
Peripherals
POR, PWM, WDT
Number Of I /o
53
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
12K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 16x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-QFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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19.7
A setting in the RAM emulation register (RAMER) enables part of RAM to overlap with the flash
memory area so that data to be written to flash memory can be emulated in RAM in real time.
Emulation can be performed in user mode or user program mode. Figure 19.7 shows an example
of emulation of real-time flash memory programming.
1. Set RAMER to overlap part of RAM with the area for which real-time programming is
2. Emulation is performed using the overlapped RAM.
3. After the program data has been confirmed, the RAMS bit is cleared, thus releasing the RAM
4. The data written in the overlapped RAM is written into the flash memory area.
required.
overlap.
Flash Memory Emulation in RAM
Figure 19.7 Flowchart for Flash Memory Emulation in RAM
No
Execute application program
Start of emulation program
End of emulation program
Write to flash memory
Write tuning data to
overlapped RAM
emulation block
Clear RAMER
Set RAMER
Tuning OK?
Yes
Rev. 2.00, 09/04, page 563 of 720
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