HD64F7047FW40V Renesas Electronics America, HD64F7047FW40V Datasheet - Page 749
HD64F7047FW40V
Manufacturer Part Number
HD64F7047FW40V
Description
MCU 5V 256K I-TEMP,PB-FREE 100-Q
Manufacturer
Renesas Electronics America
Series
SuperH® SH7047r
Datasheet
1.HD64F7047F50V.pdf
(766 pages)
Specifications of HD64F7047FW40V
Core Processor
SH-2
Core Size
32-Bit
Speed
40MHz
Connectivity
CAN, SCI
Peripherals
POR, PWM, WDT
Number Of I /o
53
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
12K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 16x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-QFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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11.1 Features
11.3.3 Reset
Control/Status Register
(RSTCSR)
Table 12.6 BRR Settings
for Various Bit Rates
(Clocked Synchronous
Mode) (1)
Table 12.6 BRR Settings
for Various Bit Rates
(Clocked Synchronous
Mode) (2)
Figure 12.5 Sample SCI
Initialization Flowchart
12.6.1 Clock
Page
317
321
346
347
355
368
Revisions (See Manual for Details)
Description amended.
•
In watchdog timer mode
•
In interval timer mode
•
•
•
RSTCSR is an 8-bit readable/writable register that controls the
generation of the internal reset signal when TCNT overflows.
Description [4] deleted.
Only in reception, the serial clock is continued generating until
an overrun error is occurred or the RE bit is cleared to 0. To
execute reception in one-character units, select an external
clock as a clock source.
Logical Bit Rate (bit/s)
1000000
2500000
Logical Bit Rate (bit/s)
5000000
Switchable between watchdog timer mode and interval
timer mode
Output WDTOVF signal
If the counter overflows, it is possible to select whether this
LSI is internally reset or not. A power-on reset or manual
reset can be selected as an in internal reset.
If the counter overflows, the WDT generates an interval
timer interrupt (ITI).
Clears software standby mode
Selectable from eight counter input clocks.
Set RIE, TIE, TEIE, and MPIE bits
Set PFC of the external pin used
Set TE and RE bits in SCR to 1
n
0
n
0
< Initialization completion>
1-bit interval elapsed?
SCK, TxD, RxD
Rev. 2.00, 09/04, page 707 of 720
Operating Frequency Pφ (MHz)
Operating Frequency Pφ (MHz)
20
4
Yes
N
0*
N
0*
Wait
n
0
n
No
[4]
[5]
10
22
N
0*
N
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