HD64F7047FW40V Renesas Electronics America, HD64F7047FW40V Datasheet - Page 518

MCU 5V 256K I-TEMP,PB-FREE 100-Q

HD64F7047FW40V

Manufacturer Part Number
HD64F7047FW40V
Description
MCU 5V 256K I-TEMP,PB-FREE 100-Q
Manufacturer
Renesas Electronics America
Series
SuperH® SH7047r
Datasheet

Specifications of HD64F7047FW40V

Core Processor
SH-2
Core Size
32-Bit
Speed
40MHz
Connectivity
CAN, SCI
Peripherals
POR, PWM, WDT
Number Of I /o
53
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
12K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 16x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-QFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

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15.4.7
The HCAN2 halt mode is provided to enable mailbox settings to be changed without performing
an HCAN2 hardware or software reset. In HCAN2 halt mode, the contents of all registers are
retained. Figure 15.14 shows a flowchart of HCAN2 halt mode.
HCAN2 halt mode is entered by setting the halt request bit (MCR1) to 1 in the master control
register (MCR). If the CAN bus is operating, the transition to HCAN2 halt mode is delayed until
the bus becomes idle.
HCAN2 halt mode is cleared by clearing MCR1 to 0.
Rev. 2.00, 09/04, page 476 of 720
HCAN2 Halt Mode
No
CAN bus communication possible
11 recessive bits received
Figure 15.14 HCAN2 Halt Mode Flowchart
Mailbox setting
GSR4 = 1?
Yes
Yes
Yes
MCR1 = 1
MCR1 = 0
Bus idle?
?
No
No
No
: Settings by user
: Processing by hardware

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