HD64F7047FW40V Renesas Electronics America, HD64F7047FW40V Datasheet - Page 430

• Manufacturer Part Number: HD64F7047FW40V
• Description: MCU 5V 256K I-TEMP,PB-FREE 100-Q
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7047r

Specifications of HD64F7047FW40V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 40MHz
• Connectivity: CAN, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

13.4.3
In single-cycle scan mode, A/D conversion is to be performed once on the specified channels
(eight channels maximum). Operations are as follows.
1. When the ADST bit in ADCR is set to 1 by a software, MTU, MMT, or external trigger input,
2. When A/D conversion for each channel is completed, the result is sequentially transferred to
3. When conversion of all the selected channels is completed, the ADF bit in ADCSR is set to 1.
4. After A/D conversion ends, the ADST bit is automatically cleared to 0 and the A/D converter
13.4.4
The A/D converter has a built-in sample-and-hold circuit for each module. The A/D converter
samples the analog input when the A/D conversion start delay time (t
bit in ADCR is set to 1, then starts conversion. Figure 13.2 shows the A/D conversion timing.
Table 13.3 shows the A/D conversion time.
As indicated in figure 13.2, the A/D conversion time (t
(t
conversion time therefore varies within the ranges indicated in table 13.3.
In scan mode, the values given in table 13.3 apply to the first conversion time. The values given
in table 13.4 apply to the second and subsequent conversions.
Rev. 2.00, 09/04, page 388 of 720
SPL
A/D conversion starts on the channel with the lowest number in the group (AN0, AN1, ...,
AN3).
the A/D data register corresponding to each channel.
If the ADIE bit is set to 1 at this time, an ADI interrupt is requested after A/D conversion ends.
enters the idle state. When the ADST bit is cleared to 0 during A/D conversion, A/D
conversion stops and the A/D converter enters the idle state.
). The length of t
Single-Cycle Scan Mode
Input Sampling and A/D Conversion Time
D
varies depending on the timing of the write access to ADCR. The total
CONV
) includes t
D
D
) has passed after the ADST
and the input sampling time