HD64F7047FW40V Renesas Electronics America, HD64F7047FW40V Datasheet - Page 273

• Manufacturer Part Number: HD64F7047FW40V
• Description: MCU 5V 256K I-TEMP,PB-FREE 100-Q
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7047r

Specifications of HD64F7047FW40V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 40MHz
• Connectivity: CAN, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

6. PWM Cycle Setting
Counter value TGRC_3
TGRA_3
In complementary PWM mode, the PWM pulse cycle is set in two registersTGRA_3, in
which the TCNT_3 upper limit value is set, and TCDR, in which the TCNT_4 upper limit
value is set. The settings should be made so as to achieve the following relationship between
these two registers:
The TGRA_3 and TCDR settings are made by setting the values in buffer registers TGRC_3
and TCBR. The values set in TGRC_3 and TCBR are transferred simultaneously to TGRA_3
and TCDR in accordance with the transfer timing selected with bits MD3–MD0 in the timer
mode register (TMDR).
The updated PWM cycle is reflected from the next cycle when the data update is performed at
the crest, and from the current cycle when performed in the trough. Figure 10.36 illustrates the
operation when the PWM cycle is updated at the crest.
See the following section, Register data updating, for the method of updating the data in each
buffer register.
TGRA_3 set value = TCDR set value + TDDR set value
update
Figure 10.36 Example of PWM Cycle Updating
TGRA_3
update
TCNT_3
TCNT_4
Rev. 2.00, 09/04, page 231 of 720
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