HD64F7047FW40V Renesas Electronics America, HD64F7047FW40V Datasheet - Page 503
HD64F7047FW40V
Manufacturer Part Number
HD64F7047FW40V
Description
MCU 5V 256K I-TEMP,PB-FREE 100-Q
Manufacturer
Renesas Electronics America
Series
SuperH® SH7047r
Datasheet
1.HD64F7047F50V.pdf
(766 pages)
Specifications of HD64F7047FW40V
Core Processor
SH-2
Core Size
32-Bit
Speed
40MHz
Connectivity
CAN, SCI
Peripherals
POR, PWM, WDT
Number Of I /o
53
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
12K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 16x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-QFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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IRR0 Clearing: The reset interrupt flag (IRR0) is always set after a power-on reset or recovery
from software standby mode. As an HCAN2 interrupt is initiated immediately when interrupts are
enabled (in the state in which the interrupt mask register (IMR0) is cleared), IRR0 should be
cleared.
LAFM setting (receive identifier mask setting)
Message transmission method setting
MB[x] setting (receive identifier setting)
MBIMR setting (interrupt mask setting)
IMR setting (interrupt mask setting)
CAN bus communication enabled
Initialization of HCAN2 module
11 recessive bits received?
MCR0 = 1 (automatic)
GSR3 = 1 (automatic)
IRR0 = 1 (automatic)
Mailbox initialization
HCAN2 port setting
Hardware reset
GSR3 = 0 &
MBC setting
BCR setting
Clear IRR0
MCR0 = 0
Set BCR
Yes
Figure 15.5 Hardware Reset Flowchart
No
Bit configuration mode
Period in which BCR, MBC, etc.,
are initialized
Rev. 2.00, 09/04, page 461 of 720
: Settings by user
: Processing by hardware
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