HD64F7047FW40V Renesas Electronics America, HD64F7047FW40V Datasheet - Page 610
HD64F7047FW40V
Manufacturer Part Number
HD64F7047FW40V
Description
MCU 5V 256K I-TEMP,PB-FREE 100-Q
Manufacturer
Renesas Electronics America
Series
SuperH® SH7047r
Datasheet
1.HD64F7047F50V.pdf
(766 pages)
Specifications of HD64F7047FW40V
Core Processor
SH-2
Core Size
32-Bit
Speed
40MHz
Connectivity
CAN, SCI
Peripherals
POR, PWM, WDT
Number Of I /o
53
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
12K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 16x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-QFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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Rev. 2.00, 09/04, page 568 of 720
Notes: * 1 Prewriting (setting erase block data to all 0s) is not necessary.
Increment address
* 2 Verify data is read in 32-bit (longword) units.
* 3 Make only a single-bit specification in the erase block register 1 (EBR1) and the erase block
* 4 Erasing is performed in block units. To erase multiple blocks, each block must be erased in turn.
register 2 (EBR2).
Figure 19.10 Erase/Erase-Verify Flowchart
No
No
Set block start address as verify address
H'FF dummy write to verify address
* 4
All erase block erased?
Last address of block?
Set EBR1 and EBR2
Verify data = all 1s?
Read verify data
Wait (t
End of erasing
SWE bit ← 1
Disable WDT
Enable WDT
ESU bit ← 1
ESU bit ← 0
SWE bit ← 0
Wait (t
Wait (t
Erase start
Wait (t
EV bit ← 1
Wait (t
Wait (t
EV bit ← 0
E bit ← 1
Wait (t
E bit ← 0
Wait (t
Wait (t
n ← 1
SSWE
CSWE
SESU
CESU
Yes
SEVR
SEV
SE
CE
CEV
) µs
Yes
Yes
)
)
)
)
)
)
)
)
* 1
No
* 3
* 2
SWE bit ← 0
Erase failure
Wait (t
EV bit ← 0
Wait (t
n ≥ N?
CSWE
CEV
Yes
)
)
No
n ← n + 1
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