HD64F7047FW40V Renesas Electronics America, HD64F7047FW40V Datasheet - Page 468
HD64F7047FW40V
Manufacturer Part Number
HD64F7047FW40V
Description
MCU 5V 256K I-TEMP,PB-FREE 100-Q
Manufacturer
Renesas Electronics America
Series
SuperH® SH7047r
Datasheet
1.HD64F7047F50V.pdf
(766 pages)
Specifications of HD64F7047FW40V
Core Processor
SH-2
Core Size
32-Bit
Speed
40MHz
Connectivity
CAN, SCI
Peripherals
POR, PWM, WDT
Number Of I /o
53
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
12K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 16x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-QFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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Rev. 2.00, 09/04, page 426 of 720
Bit
2
1
0
Bit Name
IRR2
IRR1
IRR0
Initial
Value
0
0
1
R/W
R
R
R/W
Description
Remote Frame Request Interrupt Flag
Status flag indicating that a remote frame has been
received in a mailbox.
[Setting condition]
•
[Clearing condition]
•
Receive Message Interrupt Flag
Status flag indicating that a message has been received
normally in a mailbox.
[Setting condition]
•
[Clearing condition]
•
Reset/Halt/Sleep Interrupt Flag
Status flag indicating that the HCAN2 has been reset or
halted and the HCAN2 is now in configuration mode. An
interrupt signal will be generated if the MCR0 (software
reset), MCR1 (halt), or MCR5 (sleep) bit in MCR is set to
1. GSR needs to be read after this bit is set.
1: Transition to software reset mode, halt mode, or sleep
[Clearing condition]
•
[Setting condition]
•
mode
When remote frame reception is completed and
corresponding MBIMR = 0
All bits in the remote request wait register (RFPR) are
cleared
When data frame reception is completed and
corresponding MBIMR = 0
All bits in the receive complete register (RXPR) are
cleared
Writing 1
When processing is completed after software reset
mode (MCR0), halt mode (MCR1), or sleep mode
(MCR5) is requested
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