HD64F7047FW40V Renesas Electronics America, HD64F7047FW40V Datasheet - Page 205

MCU 5V 256K I-TEMP,PB-FREE 100-Q

HD64F7047FW40V

Manufacturer Part Number
HD64F7047FW40V
Description
MCU 5V 256K I-TEMP,PB-FREE 100-Q
Manufacturer
Renesas Electronics America
Series
SuperH® SH7047r
Datasheet

Specifications of HD64F7047FW40V

Core Processor
SH-2
Core Size
32-Bit
Speed
40MHz
Connectivity
CAN, SCI
Peripherals
POR, PWM, WDT
Number Of I /o
53
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
12K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 16x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-QFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

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Part Number:
HD64F7047FW40V
0
• TIORL_0, TIORL_3, TIORL_4
Bit
7
6
5
4
3
2
1
0
Bit Name
IOD3
IOD2
IOD1
IOD0
IOC3
IOC2
IOC1
IOC0
Initial
value
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Description
I/O Control D0 to D3
Specify the function of TGRD.
When TGRD is used as the buffer register of TGRB, this
setting is disabled, and input capture/output compare does
not occur.
See the following tables.
TIORL_0: Table 10.12
TIORL_3: Table 10.20
TIORL_4: Table 10.24
I/O Control C0 to C3
Specify the function of TGRC.
When TGRC is used as the buffer register of TGRA, this
setting is disabled, and input capture/output compare does
not occur.
See the following tables.
TIORL_0: Table 10.13
TIORL_3: Table 10.21
TIORL_4: Table 10.25
Rev. 2.00, 09/04, page 163 of 720

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