HD64F7047FW40V Renesas Electronics America, HD64F7047FW40V Datasheet - Page 567
HD64F7047FW40V
Manufacturer Part Number
HD64F7047FW40V
Description
MCU 5V 256K I-TEMP,PB-FREE 100-Q
Manufacturer
Renesas Electronics America
Series
SuperH® SH7047r
Datasheet
1.HD64F7047F50V.pdf
(766 pages)
Specifications of HD64F7047FW40V
Core Processor
SH-2
Core Size
32-Bit
Speed
40MHz
Connectivity
CAN, SCI
Peripherals
POR, PWM, WDT
Number Of I /o
53
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
12K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 16x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-QFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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17.1
The registers listed below make up the pin function controller (PFC). For details on the addresses
of the registers and their states during each process, see appendix A, Internal I/O Register.
• Port A I/O register L (PAIORL)
• Port A control register L3 (PACRL3)
• Port A control register L2 (PACRL2)
• Port A control register L1 (PACRL1)
• Port B I/O register (PBIOR)
• Port B control register 1 (PBCR1)
• Port B control register 2 (PBCR2)
• Port D I/O register L (PDIORL)
• Port D control register L1 (PDCRL1)
• Port D control register L2 (PDCRL2)
• Port E I/O register H (PEIORH)
• Port E I/O register L (PEIORL)
• Port E control register H (PECRH)
• Port E control register L1 (PECRL1)
• Port E control register L2 (PECRL2)
17.1.1
The port A I/O register L (PAIORL) is a 16-bit readable/writable register that is used to set the
pins on port A as inputs or outputs. Bits PA15IOR to PA0IOR correspond to pins PA15 to PA0
(names of multiplexed pins are here given as port names and pin numbers alone). PAIORL is
enabled when the port A pins are functioning as general-purpose inputs/outputs (PA15 to PA0),
SCK2 and SCK3 pins are functioning as inputs/outputs of SCI, and PCIO pins are functioning as
an input/output of MMT. In other states, PAIORL is disabled.
A given pin on port A will be an output pin if the corresponding bit in PAIORL is set to 1, and an
input pin if the bit is cleared to 0.
The initial value of PAIORL is H'0000.
17.1.2
The port A control registers L3 to L1 (PACRL3 to PACRL1) are 16-bit readable/writable registers
that are used to select the functions of the multiplexed pins on port A.
Register Descriptions
Port A I/O Register L (PAIORL)
Port A Control Registers L3 to L1 (PACRL3 to PACRL1)
Rev. 2.00, 09/04, page 525 of 720
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