HD64F7047FW40V Renesas Electronics America, HD64F7047FW40V Datasheet - Page 99
HD64F7047FW40V
Manufacturer Part Number
HD64F7047FW40V
Description
MCU 5V 256K I-TEMP,PB-FREE 100-Q
Manufacturer
Renesas Electronics America
Series
SuperH® SH7047r
Datasheet
1.HD64F7047F50V.pdf
(766 pages)
Specifications of HD64F7047FW40V
Core Processor
SH-2
Core Size
32-Bit
Speed
40MHz
Connectivity
CAN, SCI
Peripherals
POR, PWM, WDT
Number Of I /o
53
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
12K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 16x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-QFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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5.1
5.1.1
Exception processing is started by four sources: resets, address errors, interrupts and instructions
and have the priority, as shown in table 5.1. When several exception processing sources occur at
once, they are processed according to the priority.
Table 5.1
Notes: 1. For flash version only
Exception
Reset
Address
error
Interrupt
Instructions
2. Delayed branch instructions: JMP, JSR, BRA, BSR, RTS, RTE, BF/S, BT/S, BSRF, and
3. Instructions that rewrite the PC: JMP, JSR, BRA, BSR, RTS, RTE, BT, BF, TRAPA,
Overview
Types of Exception Processing and Priority
BRAF.
BF/S, BT/S, BSRF, and BRAF.
Types of Exception Processing and Priority
Source
Power-on reset
Manual reset
CPU address error and AUD address error*
DTC address error
NMI
User break
H-UDI*
IRQ
On-chip peripheral
modules:
Trap instruction (TRAPA instruction)
General illegal instructions (undefined code)
Illegal slot instructions (undefined code placed directly after a delay
branch instruction*
1
Section 5 Exception Processing
2
or instructions that rewrite the PC*
•
•
•
•
•
•
•
•
•
•
Multifunction timer unit (MTU)
A/D converter 0 and 1 (A/D0, A/D1)
Data transfer controller (DTC)
Compare match timer 0 and 1 (CMT0, CMT1)
Watchdog timer (WDT)
Input/output port (I/O) (MTU)
Serial communication interface 2, 3, and 4 (SCI2,
SCI3, and SCI4)
Motor management timer (MMT)
Input/output port (I/O) (MMT)
Controller area network 2 (HCAN 2)
1
Rev. 2.00, 09/04, page 57 of 720
3
)
Priority
High
Low
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