HD64F7047FW40V Renesas Electronics America, HD64F7047FW40V Datasheet - Page 529
HD64F7047FW40V
Manufacturer Part Number
HD64F7047FW40V
Description
MCU 5V 256K I-TEMP,PB-FREE 100-Q
Manufacturer
Renesas Electronics America
Series
SuperH® SH7047r
Datasheet
1.HD64F7047F50V.pdf
(766 pages)
Specifications of HD64F7047FW40V
Core Processor
SH-2
Core Size
32-Bit
Speed
40MHz
Connectivity
CAN, SCI
Peripherals
POR, PWM, WDT
Number Of I /o
53
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
12K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 16x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-QFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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16.3.1
The timer mode register (MMT_TMDR) sets the operating mode and selects the PWM output
level. In this section, the name of this register is abbreviated to TMDR hereafter.
Bit
7
6
5
4
3
2
1
0
Bit Name
—
CKS2
CKS1
CKS0
OLSN
OLSP
MD1
MD0
Timer Mode Register (MMT_TMDR)
Initial
Value
0
0
0
0
0
0
0
0
R/W
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Description
Reserved
These bits are always read as 0 and should only be
written with 0.
Clock Select 2 to 0
Selects the clock input to MMT.
000: Pφ
001: Pφ/4
010: Pφ/16
011: Pφ/64
100: Pφ/256
101: Pφ/1024
11X: Setting prohibited.
Note: X “don't care”.
Output Level Select N
Selects the negative phase output level in the operating
modes.
0: Active level is low
1: Active level is high
Output Level Select P
Selects the positive phase output level in the operating
modes.
0: Active level is low
1: Active level is high
Mode 0 to 3
These bits set the timer operating mode.
00: Operation halted
01: Operating mode 1 (Transfer at TCNT = TPDR)
10: Operating mode 2 (Transfer at TCNT = TDDR × 2)
11: Operating mode 3 (Transfer at TCNT = TPDR or
TCNT = TDDR × 2)
Rev. 2.00, 09/04, page 487 of 720
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