HD64F7047FW40V Renesas Electronics America, HD64F7047FW40V Datasheet - Page 14
HD64F7047FW40V
Manufacturer Part Number
HD64F7047FW40V
Description
MCU 5V 256K I-TEMP,PB-FREE 100-Q
Manufacturer
Renesas Electronics America
Series
SuperH® SH7047r
Datasheet
1.HD64F7047F50V.pdf
(766 pages)
Specifications of HD64F7047FW40V
Core Processor
SH-2
Core Size
32-Bit
Speed
40MHz
Connectivity
CAN, SCI
Peripherals
POR, PWM, WDT
Number Of I /o
53
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
12K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 16x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-QFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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Section 8 Data Transfer Controller (DTC)........................................................ 109
8.1
8.2
8.3
8.4
8.5
Section 9 Bus State Controller (BSC) ............................................................... 133
9.1
9.2
9.3
9.4
9.5
9.6
9.7
Rev. 2.00, 09/04, page xii of xl
Features............................................................................................................................. 109
Register Descriptions........................................................................................................ 111
8.2.1
8.2.2
8.2.3
8.2.4
8.2.5
8.2.6
8.2.7
8.2.8
8.2.9
Operation .......................................................................................................................... 118
8.3.1
8.3.2
8.3.3
8.3.4
8.3.5
8.3.6
Procedures for Using DTC................................................................................................ 129
8.4.1
8.4.2
8.4.3
Cautions on Use ................................................................................................................ 131
8.5.1
8.5.2
8.5.3
Features............................................................................................................................. 133
Input/Output Pin ............................................................................................................... 135
Register Configuration...................................................................................................... 135
Address Map ..................................................................................................................... 136
Description of Registers.................................................................................................... 138
9.5.1
9.5.2
9.5.3
9.5.4
Accessing External Space ................................................................................................. 141
9.6.1
9.6.2
9.6.3
Waits between Access Cycles........................................................................................... 145
DTC Mode Register (DTMR).............................................................................. 112
DTC Source Address Register (DTSAR) ............................................................ 114
DTC Destination Address Register (DTDAR) .................................................... 114
DTC Initial Address Register (DTIAR)............................................................... 114
DTC Transfer Count Register A (DTCRA)......................................................... 114
DTC Transfer Count Register B (DTCRB) ......................................................... 114
DTC Enable Registers (DTER) ........................................................................... 115
DTC Control/Status Register (DTCSR)............................................................... 116
DTC Information Base Register (DTBR) ............................................................ 117
Activation Sources............................................................................................... 118
Location of Register Information and DTC Vector Table ................................... 118
DTC Operation .................................................................................................... 121
Interrupt Source ................................................................................................... 127
Operation Timing................................................................................................. 127
DTC Execution State Counts ............................................................................... 128
Activation by Interrupt......................................................................................... 129
Activation by Software ........................................................................................ 129
DTC Use Example............................................................................................... 130
Prohibition against DTC Register Access by DTC.............................................. 131
Module Standby Mode Setting ............................................................................ 131
On-Chip RAM ..................................................................................................... 131
Bus Control Register 1 (BCR1) ........................................................................... 138
Bus Control Register 2 (BCR2) ........................................................................... 139
Wait Control Register 1 (WCR1) ........................................................................ 140
RAM Emulation Register (RAMER)................................................................... 140
Basic Timing........................................................................................................ 141
Wait State Control ............................................................................................... 142
CS Assert Period Extension................................................................................. 144
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