HD64F7047FW40V Renesas Electronics America, HD64F7047FW40V Datasheet - Page 274
HD64F7047FW40V
Manufacturer Part Number
HD64F7047FW40V
Description
MCU 5V 256K I-TEMP,PB-FREE 100-Q
Manufacturer
Renesas Electronics America
Series
SuperH® SH7047r
Datasheet
1.HD64F7047F50V.pdf
(766 pages)
Specifications of HD64F7047FW40V
Core Processor
SH-2
Core Size
32-Bit
Speed
40MHz
Connectivity
CAN, SCI
Peripherals
POR, PWM, WDT
Number Of I /o
53
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
12K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 16x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-QFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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7. Register Data Updating
Rev. 2.00, 09/04, page 232 of 720
In complementary PWM mode, the buffer register is used to update the data in a compare
register. The update data can be written to the buffer register at any time. There are five PWM
duty and carrier cycle registers that have buffer registers and can be updated during operation.
There is a temporary register between each of these registers and its buffer register. When
subcounter TCNTS is not counting, if buffer register data is updated, the temporary register
value is also rewritten. Transfer is not performed from buffer registers to temporary registers
when TCNTS is counting; in this case, the value written to a buffer register is transferred after
TCNTS halts.
The temporary register value is transferred to the compare register at the data update timing set
with bits MD3–MD0 in the timer mode register (TMDR). Figure 10.37 shows an example of
data updating in complementary PWM mode. This example shows the mode in which data
updating is performed at both the counter crest and trough.
When rewriting buffer register data, a write to TGRD_4 must be performed at the end of the
update. Data transfer from the buffer registers to the temporary registers is performed
simultaneously for all five registers after the write to TGRD_4.
A write to TGRD_4 must be performed after writing data to the registers to be updated, even
when not updating all five registers, or when updating the TGRD_4 data. In this case, the data
written to TGRD_4 should be the same as the data prior to the write operation.
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