HD64F7047FW40V Renesas Electronics America, HD64F7047FW40V Datasheet - Page 371

• Manufacturer Part Number: HD64F7047FW40V
• Description: MCU 5V 256K I-TEMP,PB-FREE 100-Q
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7047r

Specifications of HD64F7047FW40V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 40MHz
• Connectivity: CAN, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

This LSI has three independent serial communication interface (SCI) channels. The SCI can
handle both asynchronous and clocked synchronous serial communication. In asynchronous serial
communication mode, serial data communication can be carried out with standard asynchronous
communication chips such as a Universal Asynchronous Receiver/Transmitter (UART) or
Asynchronous Communication Interface Adapter (ACIA). A function is also provided for serial
communication between processors (multiprocessor communication function).
12.1
• Choice of asynchronous or clocked synchronous serial communication mode
• Full-duplex communication capability
• On-chip baud rate generator allows any bit rate to be selected
• Choice of LSB-first or MSB-first transfer (except in the case of asynchronous mode 7-bit data)
• Four interrupt sources
• Module standby mode can be set
Asynchronous mode
• Data length: 7 or 8 bits
• Stop bit length: 1 or 2 bits
• Parity: Even, odd, or none
• Multiprocessor bit: 1 or 0
• Receive error detection: Parity, overrun, and framing errors
• Break detection: Break can be detected by reading the RxD pin level directly in case of a
The transmitter and receiver are mutually independent, enabling transmission and reception to
be executed simultaneously.
Double-buffering is used in both the transmitter and the receiver, enabling continuous
transmission and continuous reception of serial data.
External clock can be selected as a transfer clock source.
Four interrupt sources  transmit-end, transmit-data-empty, receive-data-full, and receive
error  that can issue requests.
The transmit-data-empty interrupt and receive data full interrupts can activate the data transfer
controller (DTC).
framing error
Section 12 Serial Communication Interface (SCI)
Features
Rev. 2.00, 09/04, page 329 of 720