HD64F7047FW40V Renesas Electronics America, HD64F7047FW40V Datasheet - Page 362
HD64F7047FW40V
Manufacturer Part Number
HD64F7047FW40V
Description
MCU 5V 256K I-TEMP,PB-FREE 100-Q
Manufacturer
Renesas Electronics America
Series
SuperH® SH7047r
Datasheet
1.HD64F7047F50V.pdf
(766 pages)
Specifications of HD64F7047FW40V
Core Processor
SH-2
Core Size
32-Bit
Speed
40MHz
Connectivity
CAN, SCI
Peripherals
POR, PWM, WDT
Number Of I /o
53
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
12K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 16x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-QFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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Notes: 1. Only a 0 can be written after reading 1.
Rev. 2.00, 09/04, page 320 of 720
Bit
6
5
4, 3
2
1
0
2. Section 11.3.3, Reset Control/Status Register (RSTCSR), describes in detail what
3. The overflow interval listed is the time from when the TCNT begins counting at H'00
Bit Name
WT/IT
CKS2
CKS1
CKS0
TME
happens when TCNT overflows in watchdog timer mode.
until an overflow occurs.
0
Initial
Value
0
All 1
0
0
0
R/W
R/W
R/W
R
R/W
R/W
R/W
Description
Timer Mode Select
Selects whether the WDT is used as a watchdog
timer or interval timer. When TCNT overflows, the
WDT either generates an interval timer interrupt (ITI)
or generates a WDTOVF signal, depending on the
mode selected.
0: Interval timer mode
1: Watchdog timer mode
Timer Enable
Enables or disables the timer.
0: Timer disabled
1: Timer enabled
Reserved
This bit is always read as 1, and should only be
written with 1.
Clock Select 2 to 0
Select one of eight internal clock sources for input to
TCNT. The clock signals are obtained by dividing the
frequency of the system clock (
frequency for φ = 40 MHz is enclosed in
parentheses*
000: Clock φ/2 (period: 12.8 µs)
001: Clock φ/64 (period: 409.6 µs)
010: Clock φ/128 (period: 0.8 ms)
011: Clock φ/256 (period: 1.6 ms)
100: Clock φ/512 (period: 3.3 ms)
101: Clock φ/1024 (period: 6.6 ms)
110: Clock φ/4096 (period: 26.2 ms)
111: Clock φ/8192 (period: 52.4 ms)
Interval timer interrupt (ITI) request to the CPU
when TCNT overflows
WDTOVF signal output externally when TCNT
overflows*
TCNT is initialized to H'00 and count-up stops
TCNT starts counting. A WDTOVF signal or
interrupt is generated when TCNT overflows.
2
3
.
.
φ
). The overflow
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