HD64F7047FW40V Renesas Electronics America, HD64F7047FW40V Datasheet - Page 161
HD64F7047FW40V
Manufacturer Part Number
HD64F7047FW40V
Description
MCU 5V 256K I-TEMP,PB-FREE 100-Q
Manufacturer
Renesas Electronics America
Series
SuperH® SH7047r
Datasheet
1.HD64F7047F50V.pdf
(766 pages)
Specifications of HD64F7047FW40V
Core Processor
SH-2
Core Size
32-Bit
Speed
40MHz
Connectivity
CAN, SCI
Peripherals
POR, PWM, WDT
Number Of I /o
53
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
12K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 16x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-QFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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Figure 8.4 shows the correspondence between DTC vector addresses and register information
allocation. For each DTC activating source there are 2 bytes in the DTC vector table, which
contain the register information start address.
Table 8.1 shows the correspondence between activating sources and vector addresses. When
activating with software, the vector address is calculated as H'0400 + DTVEC[7:0].
Through DTC activation, a register information start address is read from the vector table, then
register information placed in memory space is read from that register information start address.
Always designate register information start addresses in multiples of four.
Figure 8.4 Correspondence between DTC Vector Address and Transfer Information
Register
information
start address
DTC vector address
Figure 8.3 DTC Register Information Allocation in Memory Space
Memory space
Normal mode
DTCRA
DTSAR
DTDAR
DTMR
Transfer information
Register information
DTC vector table
(lower 16 bits)
(upper 16 bits)
start address
start address
DTBR
Memory space
Repeat mode
DTCRA
DTSAR
DTDAR
DTIAR
DTMR
Block transfer mode
Memory space
Rev. 2.00, 09/04, page 119 of 720
DTCRA
DTCRB
DTSAR
DTDAR
DTMR
Memory space
information
Register
Register
information
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