AT91SAM9G45-CU-999 Atmel, AT91SAM9G45-CU-999 Datasheet - Page 1054
AT91SAM9G45-CU-999
Manufacturer Part Number
AT91SAM9G45-CU-999
Description
IC MCU ARM9 APMC 324TFBGA
Manufacturer
Atmel
Series
AT91SAMr
Datasheet
1.AT91SAM9G45-EKES.pdf
(1218 pages)
Specifications of AT91SAM9G45-CU-999
Core Processor
ARM9
Core Size
16/32-Bit
Speed
400MHz
Connectivity
EBI/EMI, Ethernet, I²C, IrDA, MMC, SPI, SSC, UART/USART, USB
Peripherals
AC'97, DMA, I²S, LCD, POR, PWM, WDT
Number Of I /o
160
Program Memory Size
64KB (64K x 8)
Program Memory Type
ROM
Ram Size
128K x 8
Voltage - Supply (vcc/vdd)
0.9 V ~ 1.1 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
324-TFBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Supplier Unconfirmed
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43.6
43.6.1
43.6.2
43.6.3
1054
Product Dependencies
AT91SAM9G45
I/O Lines
Power Management
Interrupt
The pins used for interfacing the compliant external devices may be multiplexed with PIO lines.
Before using the AC97 Controller receiver, the PIO controller must be configured in order for the
AC97C receiver I/O lines to be in AC97 Controller peripheral mode.
Before using the AC97 Controller transmitter, the PIO controller must be configured in order for
the AC97C transmitter I/O lines to be in AC97 Controller peripheral mode.
Table 43-2.
The AC97 Controller is not continuously clocked. Its interface may be clocked through the Power
Management Controller (PMC), therefore the programmer must first configure the PMC to
enable the AC97 Controller clock.
The AC97 Controller has two clock domains. The first one is supplied by PMC and is equal to
MCK. The second one is AC97CK which is sent by the AC97 Codec (Bit clock).
Signals that cross the two clock domains are re-synchronized. MCK clock frequency must be
higher than the AC97CK (Bit Clock) clock frequency.
The AC97 Controller interface has an interrupt line connected to the Advanced Interrupt Control-
ler (AIC). Handling interrupts requires programming the AIC before configuring the AC97C.
All AC97 Controller interrupts can be enabled/disabled by writing to the AC97 Controller Inter-
rupt Enable/Disable Registers. Each pending and unmasked AC97 Controller interrupt will
assert the interrupt line. The AC97 Controller interrupt service routine can get the interrupt
source in two steps:
Table 43-3.
• Reading and ANDing AC97 Controller Interrupt Mask Register (AC97C_IMR) and AC97
• Reading AC97 Controller Channel x Status Register (AC97C_CxSR).
Controller Status Register (AC97C_SR).
Instance
Instance
AC97C
AC97C
AC97C
AC97C
AC97C
I/O Lines
Peripheral IDs
24
ID
AC97CK
AC97RX
AC97FS
AC97TX
Signal
I/O Line
PD9
PD8
PD6
PD7
6438F–ATARM–21-Jun-10
Peripheral
A
A
A
A
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