AT91SAM9G45-CU-999 Atmel, AT91SAM9G45-CU-999 Datasheet - Page 982

• Manufacturer Part Number: AT91SAM9G45-CU-999
• Description: IC MCU ARM9 APMC 324TFBGA
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91SAM9G45-CU-999

• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 400MHz
• Connectivity: EBI/EMI, Ethernet, I²C, IrDA, MMC, SPI, SSC, UART/USART, USB
• Peripherals: AC'97, DMA, I²S, LCD, POR, PWM, WDT
• Number Of I /o: 160
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: ROM
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 0.9 V ~ 1.1 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 324-TFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Supplier Unconfirmed

41.4.4.3
Table 41-2.
Notes:
41.4.4.4
41.4.4.5
6438F–ATARM–21-Jun-10
BTSIZE, SADDR reloaded
with BTSIZE reloaded and
with BTSIZE reloaded and
buffer of a multiple buffer
with contiguous DADDR
with contiguous SADDR
and DADDR contiguous
1) Single Buffer or Last
2) Multi Buffer transfer
3) Multi Buffer transfer
4) Multi Buffer transfer
5) Multi Buffer transfer
6) Multi Buffer transfer
7) Multi Buffer transfer
8) Multi Buffer transfer
with DADDR reloaded
with SADDR reloaded
BTSIZE, SADDR and
10) Automatic mode
11) Automatic mode
contiguous DADDR
contiguous SADDR
9) Automatic mode
BTsize is reloaded
channel is stalling
DADDR reloaded
with LLI support
Transfer Type
1. USR means that the register field is manually programmed by the user.
2. CONT means that address are contiguous.
3. REP means that the register field is updated with its previous value. If the transfer is the first one, then the user must manu-
4. Channel stalled is true if the relevant BTC interrupt is not masked.
5. LLI means that the register field is updated with the content of the linked list item.
transfer
ally program the value.
Replay Mode of Channel Registers
Contiguous Address Between Buffers
Programming DMAC for Multiple Buffer Transfers
Multiple Buffers Transfer Management Table
AUTO
During automatic replay mode, the channel registers are reloaded with their initial values at the
completion of each buffer and the new values used for the new buffer. Depending on the row
number in
DMAC_CTRLAx and DMAC_CTRLBx channel registers are reloaded from their initial value at
the start of a buffer transfer.
In this case, the address between successive buffers is selected to be a continuation from the
end of the previous buffer. Enabling the source or destination address to be contiguous between
0
0
0
0
0
0
1
1
1
1
1
SRC_REP
–
–
0
–
–
1
–
0
0
1
1
Table 41-2 on page
DST_REP
–
0
–
–
1
–
0
–
0
1
0
SRC_DSCR
982, some or all of the DMAC_SADDRx, DMAC_DADDRx,
1
0
1
0
0
1
0
1
1
1
1
DST_DSCR
1
1
0
0
1
0
1
0
1
1
1
BTSIZE
USR
REP
REP
REP
REP
REP
LLI
LLI
LLI
LLI
LLI
SADDR
CONT
CONT
CONT
USR
REP
REP
REP
AT91SAM9G45
LLI
LLI
LLI
LLI
DADDR
CONT
CONT
CONT
CONT
USR
REP
REP
LLI
LLI
LLI
LLI
Fields
Other
USR
REP
REP
REP
LLI
LLI
LLI
LLI
LLI
LLI
LLI
982