AT91SAM9G45-CU-999 Atmel, AT91SAM9G45-CU-999 Datasheet - Page 277

• Manufacturer Part Number: AT91SAM9G45-CU-999
• Description: IC MCU ARM9 APMC 324TFBGA
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91SAM9G45-CU-999

• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 400MHz
• Connectivity: EBI/EMI, Ethernet, I²C, IrDA, MMC, SPI, SSC, UART/USART, USB
• Peripherals: AC'97, DMA, I²S, LCD, POR, PWM, WDT
• Number Of I /o: 160
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: ROM
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 0.9 V ~ 1.1 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 324-TFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Supplier Unconfirmed

23. Peripheral DMA Controller (PDC)
23.1
23.2
6438F–ATARM–21-Jun-10
Description
Embedded Characteristics
The Peripheral DMA Controller (PDC) transfers data between on-chip serial peripherals and the
on- and/or off-chip memories. The link between the PDC and a serial peripheral is operated by
the AHB to ABP bridge.
The user interface of each PDC channel is integrated into the user interface of the peripheral it
serves. The user interface of mono directional channels (receive only or transmit only), contains
two 32-bit memory pointers and two 16-bit counters, one set (pointer, counter) for current trans-
fer and one set (pointer, counter) for next transfer. The bi-directional channel user interface
contains four 32-bit memory pointers and four 16-bit counters. Each set (pointer, counter) is
used by current transmit, next transmit, current receive and next receive.
Using the PDC removes processor overhead by reducing its intervention during the transfer.
This significantly reduces the number of clock cycles required for a data transfer, which
improves microcontroller performance.
To launch a transfer, the peripheral triggers its associated PDC channels by using transmit and
receive signals. When the programmed data is transferred, an end of transfer interrupt is gener-
ated by the peripheral itself.
The Peripheral DMA Controller handles transfer requests from the channel according to the fol-
lowing priorities (Low to High priorities):
Table 23-1.
Instance name
DBGU
USART3
USART2
USART1
USART0
AC97C
SPI1
SPI0
SSC1
SSC0
TSADCC
DBGU
USART3
• Acting as one AHB Bus Matrix Master
• Allows data transfers from/to peripheral to/from any memory space without any intervention
• Next Pointer support, prevents strong real-time constraints on buffer management.
of the processor.
Peripheral DMA Controller
Channel T/R
Transmit
Transmit
Transmit
Transmit
Transmit
Transmit
Transmit
Transmit
Transmit
Transmit
Receive
Receive
Receive
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