AT91SAM9G45-CU-999 Atmel, AT91SAM9G45-CU-999 Datasheet - Page 61

• Manufacturer Part Number: AT91SAM9G45-CU-999
• Description: IC MCU ARM9 APMC 324TFBGA
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91SAM9G45-CU-999

• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 400MHz
• Connectivity: EBI/EMI, Ethernet, I²C, IrDA, MMC, SPI, SSC, UART/USART, USB
• Peripherals: AC'97, DMA, I²S, LCD, POR, PWM, WDT
• Number Of I /o: 160
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: ROM
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 0.9 V ~ 1.1 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 324-TFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Supplier Unconfirmed

11.4.2
11.4.2.1
6438F–ATARM–21-Jun-10
Valid Code Detection
ARM Exception Vectors Check
Figure 11-3. Remap Action after Download Completion
The NVM bootloader program initializes the NVM. It initializes the required PIO. It sets the right
peripheral depending on the NVM and tries to access the memory. If the initialization fails, it
restores the reset values for the PIO and peripherals and then the next NVM bootloader program
is executed.
If the initialization is successful, the NVM bootloader program reads the beginning of the NVM
and determines if the NVM contains valid code.
If the NVM does not contain valid code, the NVM bootloader program restores the reset value for
the peripherals and then the next NVM bootloader program is executed.
If valid code is found, this code is loaded from NVM into internal SRAM and executed by branch-
ing at address 0x0000_0000 after remap. This code may be the application code or a second-
level bootloader. All the calls to functions are PC relative and do not use absolute addresses.
There are two kinds of valid code detection. Depending on the NVM bootloader, either one or
both of them is used.
The NVM bootloader program reads and analyzes the first 28 bytes corresponding to the first
seven ARM exception vectors. Except for the sixth vector, these bytes must implement the ARM
instructions for either branch or load PC with PC relative addressing.
Figure 11-4. LDR Opcode
31
1
1
1
28 27
0
0x0000_0000
0x0030_0000
0x0040_0000
0
1
I
24 23
P
U
Internal
Internal
Internal
ROM
SRAM
ROM
1
W 0
20 19
Rn
REMAP
16 15
Rd
Internal
Internal
Internal
SRAM
SRAM
ROM
12 11
AT91SAM9G45
0x0000_0000
0x0030_0000
0x0040_0000
O set
0
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