AT91SAM9G45-CU-999 Atmel, AT91SAM9G45-CU-999 Datasheet - Page 563
![IC MCU ARM9 APMC 324TFBGA](/photos/12/13/121367/324-tfbga-pkg_sml.jpg)
AT91SAM9G45-CU-999
Manufacturer Part Number
AT91SAM9G45-CU-999
Description
IC MCU ARM9 APMC 324TFBGA
Manufacturer
Atmel
Series
AT91SAMr
Datasheet
1.AT91SAM9G45-EKES.pdf
(1218 pages)
Specifications of AT91SAM9G45-CU-999
Core Processor
ARM9
Core Size
16/32-Bit
Speed
400MHz
Connectivity
EBI/EMI, Ethernet, I²C, IrDA, MMC, SPI, SSC, UART/USART, USB
Peripherals
AC'97, DMA, I²S, LCD, POR, PWM, WDT
Number Of I /o
160
Program Memory Size
64KB (64K x 8)
Program Memory Type
ROM
Ram Size
128K x 8
Voltage - Supply (vcc/vdd)
0.9 V ~ 1.1 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
324-TFBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Supplier Unconfirmed
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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33.6
33.6.1
33.6.2
6438F–ATARM–21-Jun-10
Product Dependencies
I/O Lines
Power Management
The pins used for interfacing the USART may be multiplexed with the PIO lines. The program-
mer must first program the PIO controller to assign the desired USART pins to their peripheral
function. If I/O lines of the USART are not used by the application, they can be used for other
purposes by the PIO Controller.
To prevent the TXD line from falling when the USART is disabled, the use of an internal pull up
is mandatory. If the hardware handshaking feature is used, the internal pull up on TXD must
also be enabled.
Table 33-3.
The USART is not continuously clocked. The programmer must first enable the USART Clock in
the Power Management Controller (PMC) before using the USART. However, if the application
does not require USART operations, the USART clock can be stopped when not needed and be
restarted later. In this case, the USART will resume its operations where it left off.
Configuring the USART does not require the USART clock to be enabled.
Instance
USART0
USART0
USART0
USART0
USART0
USART1
USART1
USART1
USART1
USART1
USART2
USART2
USART2
USART2
USART2
USART3
USART3
USART3
USART3
USART3
I/O Lines
Signal
RXD0
RXD1
RXD2
RXD3
CTS0
RTS0
SCK0
TXD0
CTS1
RTS1
SCK1
TXD1
CTS2
RTS2
SCK2
TXD2
CTS3
RTS3
SCK3
TXD3
I/O Line
PD17
PC11
PB15
PB17
PB18
PB16
PB19
PD16
PD29
PD30
AT91SAM9G45
PA24
PA23
PA22
PB5
PB4
PC9
PB7
PB6
PB9
PB8
Peripheral
B
B
A
B
A
A
A
A
B
A
B
B
A
B
A
B
B
A
B
A
563
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