AT91SAM9G45-CU-999 Atmel, AT91SAM9G45-CU-999 Datasheet - Page 973
AT91SAM9G45-CU-999
Manufacturer Part Number
AT91SAM9G45-CU-999
Description
IC MCU ARM9 APMC 324TFBGA
Manufacturer
Atmel
Series
AT91SAMr
Datasheet
1.AT91SAM9G45-EKES.pdf
(1218 pages)
Specifications of AT91SAM9G45-CU-999
Core Processor
ARM9
Core Size
16/32-Bit
Speed
400MHz
Connectivity
EBI/EMI, Ethernet, I²C, IrDA, MMC, SPI, SSC, UART/USART, USB
Peripherals
AC'97, DMA, I²S, LCD, POR, PWM, WDT
Number Of I /o
160
Program Memory Size
64KB (64K x 8)
Program Memory Type
ROM
Ram Size
128K x 8
Voltage - Supply (vcc/vdd)
0.9 V ~ 1.1 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
324-TFBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Supplier Unconfirmed
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Part Number
Manufacturer
Quantity
Price
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41. DMA Controller (DMAC)
41.1
41.2
6438F–ATARM–21-Jun-10
Description
Embedded Characteristics
The DMA Controller (DMAC) is an AHB-central DMA controller core that transfers data from a
source peripheral to a destination peripheral over one or more AMBA buses. One channel is
required for each source/destination pair. In the most basic configuration, the DMAC has one
master interface and one channel. The master interface reads the data from a source and writes
it to a destination. Two AMBA transfers are required for each DMAC data transfer. This is also
known as a dual-access transfer.
The DMAC is programmed via the APB interface.
The DMA controller can handle the transfer between peripherals and memory and so receives
the triggers from the peripherals below. The hardware interface numbers are also given below in
Table 41-1
Table 41-1.
Instance Name
MCI0
SPI0
SPI0
SPI1
SPI1
SSC0
SSC0
SSC1
SSC1
AC97C
AC97C
MCI1
• Two Masters
• Embeds 8 channels
• 64 bytes/FIFO for Channel Buffering
• Linked List support with Status Write Back operation at End of Transfer
• Word, HalfWord, Byte transfer support.
• memory to memory transfer
• Peripheral to memory
• Memory to peripheral
• Acting as two Matrix Masters
• Embeds 8 unidirectional channels with programmable priority
DMA Channel Definition
T/R
TX/RX
TX
RX
TX
RX
TX
RX
TX
RX
TX
RX
TX/RX
DMA Channel HW
interface Number
0
1
2
3
4
5
6
7
8
9
10
13
AT91SAM9G45
973
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