AT91SAM9G45-CU-999 Atmel, AT91SAM9G45-CU-999 Datasheet - Page 1106

IC MCU ARM9 APMC 324TFBGA

AT91SAM9G45-CU-999

Manufacturer Part Number
AT91SAM9G45-CU-999
Description
IC MCU ARM9 APMC 324TFBGA
Manufacturer
Atmel
Series
AT91SAMr
Datasheet

Specifications of AT91SAM9G45-CU-999

Core Processor
ARM9
Core Size
16/32-Bit
Speed
400MHz
Connectivity
EBI/EMI, Ethernet, I²C, IrDA, MMC, SPI, SSC, UART/USART, USB
Peripherals
AC'97, DMA, I²S, LCD, POR, PWM, WDT
Number Of I /o
160
Program Memory Size
64KB (64K x 8)
Program Memory Type
ROM
Ram Size
128K x 8
Voltage - Supply (vcc/vdd)
0.9 V ~ 1.1 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
324-TFBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Supplier Unconfirmed

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Part Number:
AT91SAM9G45-CU-999
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AT91SAM9G45
Table 45-11
Table 45-11. Dithering Duty Cycle
The duty cycles for gray levels 0 and 15 are 0 and 1, respectively.
The same DP_i register can be used for the pairs for which the sum of duty cycles is 1 (e.g., 1/7
and 6/7). The dithering pattern for the first pair member is the inversion of the one for the
second.
The DP_i registers contain a series of 4-bit patterns. The (3-m)
pixel with horizontal coordinate x = 4n + m (n is an integer and m ranges from 0 to 3) should be
turned on or off in the current frame. The operation is shown by the examples below.
Consider the pixels a, b, c and d with the horizontal coordinates 4*n+0, 4*n+1, 4*n+2 and 4*n+3,
respectively. The four pixels should be displayed in gray level 9 (duty cycle 3/5) so the register
used is DP3_5 =”1010 0101 1010 0101 1111”.
The output sequence obtained in the data output for monochrome mode is shown in
12.
Table 45-12. Dithering Algorithm for Monochrome Mode
Gray Level
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Frame
Number
N
N+1
N+2
N+3
shows the correspondences between the gray levels and the duty cycle.
Pattern
1010
0101
1010
0101
Duty Cycle
1
6/7
4/5
3/4
5/7
2/3
3/5
4/7
1/2
3/7
2/5
1/3
1/4
1/5
1/7
0
Pixel a
ON
OFF
ON
OFF
Pixel b
OFF
ON
OFF
ON
th
bit of the pattern determines if a
Pattern Register
-
DP6_7
DP4_5
DP3_4
DP5_7
DP2_3
DP3_5
DP4_7
~DP1_2
~DP4_7
~DP3_5
~DP2_3
~DP3_4
~DP4_5
~DP6_7
-
Pixel c
ON
OFF
ON
OFF
6438F–ATARM–21-Jun-10
Pixel d
OFF
ON
OFF
ON
Table 45-

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