AT91SAM9G45-CU-999 Atmel, AT91SAM9G45-CU-999 Datasheet - Page 995
AT91SAM9G45-CU-999
Manufacturer Part Number
AT91SAM9G45-CU-999
Description
IC MCU ARM9 APMC 324TFBGA
Manufacturer
Atmel
Series
AT91SAMr
Datasheet
1.AT91SAM9G45-EKES.pdf
(1218 pages)
Specifications of AT91SAM9G45-CU-999
Core Processor
ARM9
Core Size
16/32-Bit
Speed
400MHz
Connectivity
EBI/EMI, Ethernet, I²C, IrDA, MMC, SPI, SSC, UART/USART, USB
Peripherals
AC'97, DMA, I²S, LCD, POR, PWM, WDT
Number Of I /o
160
Program Memory Size
64KB (64K x 8)
Program Memory Type
ROM
Ram Size
128K x 8
Voltage - Supply (vcc/vdd)
0.9 V ~ 1.1 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
324-TFBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Supplier Unconfirmed
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Manufacturer
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Figure 41-12. DMAC Transfer Flow for Replay Mode at Source and Linked List Destination Address
41.4.5.6
6438F–ATARM–21-Jun-10
Multi-buffer Transfer with Source Address Auto-reloaded and Contiguous Destination Address (Row 11)
HDMA Transfer Complete
interrupt generated here
1. Read the Channel Enable register to choose a free (disabled) channel.
2. Clear any pending interrupts on the channel from the previous DMAC transfer by read-
3. Program the following channel registers:
ing to the Interrupt Status Register.
a. Write the starting source address in the DMAC_SADDRx register for channel x.
b. Write the starting destination address in the DMAC_DADDRx register for channel
c. Program DMAC_CTRLAx, DMAC_CTRLBx and DMAC_CFGx according to Row
d. Write the control information for the DMAC transfer in the DMAC_CTRLBx and
– i. Set up the transfer type (memory or non-memory peripheral for source and
destination) and flow control device by programming the FC of the DMAC_CTRLBx
register.
x.
11 as shown in
‘0’. DMAC_CTRLBx.AUTO field is set to ‘1’ to enable automatic mode support.
DMAC_CTRLAx register for channel x. For example, in this register, you can pro-
gram the following:
Buffer Complete interrupt
generated here
Channel Disabled by
hardware
Table 41-2 on page
yes
DADDRx, CTRLAx, CTRLBx, DSCRx
HDMA State Machine Table?
status information in LLI
Hardware reprograms
Writeback of control
Channel Enabled by
DMA buffer transfer
Reload SADDRx
Is HDMA in
982. Program the DMAC_DSCRx register with
LLI Fetch
Row1 of
software
no
AT91SAM9G45
995
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