AT91SAM9G45-CU-999 Atmel, AT91SAM9G45-CU-999 Datasheet - Page 899
![IC MCU ARM9 APMC 324TFBGA](/photos/12/13/121367/324-tfbga-pkg_sml.jpg)
AT91SAM9G45-CU-999
Manufacturer Part Number
AT91SAM9G45-CU-999
Description
IC MCU ARM9 APMC 324TFBGA
Manufacturer
Atmel
Series
AT91SAMr
Datasheet
1.AT91SAM9G45-EKES.pdf
(1218 pages)
Specifications of AT91SAM9G45-CU-999
Core Processor
ARM9
Core Size
16/32-Bit
Speed
400MHz
Connectivity
EBI/EMI, Ethernet, I²C, IrDA, MMC, SPI, SSC, UART/USART, USB
Peripherals
AC'97, DMA, I²S, LCD, POR, PWM, WDT
Number Of I /o
160
Program Memory Size
64KB (64K x 8)
Program Memory Type
ROM
Ram Size
128K x 8
Voltage - Supply (vcc/vdd)
0.9 V ~ 1.1 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
324-TFBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Supplier Unconfirmed
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Part Number
Manufacturer
Quantity
Price
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Table 39-3.
Table 39-4.
Table 39-5.
39.4.3
6438F–ATARM–21-Jun-10
RGB 5:6:5
Mode
RGB 5:6:5
Mode
RGB 8:8:8
RGB 5:6:5
Clocks
RGB Format in Default Mode, RGB_CFG = 00, No Swap
RGB Format, RGB_CFG = 10 (Mode 2), No Swap
RGB Format in Default Mode, RGB_CFG = 00, Swap Activated
Byte 0
Byte 1
Byte 2
Byte 3
Byte
Byte 0
Byte 1
Byte 2
Byte 3
Byte
Byte 0
Byte 1
Byte 2
Byte 3
Byte 0
Byte 1
Byte 2
Byte 3
The RGB 5:6:5 input format is processed to be displayed as RGB 5:6:5 format, compliant with
the 16-bit mode of the LCD controller.
The sensor master clock (ISI_MCK) can be generated either by the Advanced Power Manage-
ment Controller (APMC) through a Programmable Clock output or by an external oscillator
connected to the sensor.
None of the sensors embed a power management controller, so providing the clock by the
APMC is a simple and efficient way to control power consumption of the system.
Care must be taken when programming the system clock. The ISI has two clock domains, the
system bus clock and the pixel clock provided by sensor. The two clock domains are not syn-
chronized, but the system clock must be faster than pixel clock.
R4(i)
G2(i)
R4(i+1)
G2(i+1)
D7
G2(i)
B4(i)
G2(i+1)
B4(i+1)
D7
R0(i)
G0(i)
B0(i)
R0(i+1)
G3(i)
B0(i)
G3(i+1)
B0(i+1)
R3(i)
G1(i)
R3(i+1)
G1(i+1)
D6
G1(i)
B3(i)
G1(i+1)
B3(i+1)
D6
R1(i)
G1(i)
B1(i)
R1(i+1)
G4(i)
B1(i)
G4(i+1)
B1(i+1)
R2(i)
R2(i+1)
G0(i)
G0(i+1)
D5
G0(i)
B2(i)
G0(i+1)
B2(i+1)
D5
R2(i)
G2(i)
B2(i)
R2(i+1)
G5(i)
B2(i)
G5(i+1)
B2(i+1)
R1(i)
R1(i+1)
B4(i)
B4(i+1)
D4
R4(i)
B1(i)
R4(i+1)
B1(i+1)
D4
R3(i)
G3(i)
B3(i)
R3(i+1)
R0(i)
B3(i)
R0(i+1)
B3(i+1)
R0(i)
B3(i)
R0(i+1)
B3(i+1)
D3
R3(i)
B0(i)
R3(i+1)
B0(i+1)
D3
R4(i)
G4(i)
B4(i)
R4(i+1)
R1(i)
B4(i)
R1(i+1)
B4(i+1)
G5(i)
G5(i+1)
B2(i)
B2(i+1)
D2
R2(i)
G5(i)
R2(i+1)
G5(i+1)
D2
R5(i)
G5(i)
B5(i)
R5(i+1)
R2(i)
G0(i)
R2(i+1)
G0(i+1)
AT91SAM9G45
G4(i)
B1(i)
G4(i+1)
B1(i+1)
D1
R1(i)
G4(i)
R1(i+1)
G4(i+1)
D1
R6(i)
G6(i)
B6(i)
R6(i+1)
R3(i)
G1(i)
R3(i+1)
G1(i+1)
G3(i)
B0(i)
G3(i+1)
B0(i+1)
R0(i)
R0(i+1)
G3(i+1)
G7(i)
R4(i)
R4(i+1)
G2(i+1)
D0
G3(i)
D0
R7(i)
B7(i)
R7(i+1)
G2(i)
899
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