AT91SAM9G45-CU-999 Atmel, AT91SAM9G45-CU-999 Datasheet - Page 992

• Manufacturer Part Number: AT91SAM9G45-CU-999
• Description: IC MCU ARM9 APMC 324TFBGA
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91SAM9G45-CU-999

• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 400MHz
• Connectivity: EBI/EMI, Ethernet, I²C, IrDA, MMC, SPI, SSC, UART/USART, USB
• Peripherals: AC'97, DMA, I²S, LCD, POR, PWM, WDT
• Number Of I /o: 160
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: ROM
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 0.9 V ~ 1.1 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 324-TFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Supplier Unconfirmed

Figure 41-10. DMAC Transfer Flow for Source and Destination Address Auto-reloaded
41.4.5.5
6438F–ATARM–21-Jun-10
Multi-buffer Transfer with Source Address Auto-reloaded and Linked List Destination Address (Row 6)
HDMA Transfer Complete
Interrupt generated here
1. Read the Channel Enable register to choose a free (disabled) channel.
2. Set up the chain of linked list items (otherwise known as buffer descriptors) in memory.
Write the control information in the LLI.DMAC_CTRLAx and DMAC_CTRLBx registers
location of the buffer descriptor for each LLI in memory for channel x. For example, in
the register you can program the following:
a. Set up the transfer type (memory or non-memory peripheral for source and desti-
b. Set up the transfer characteristics, such as:
– i. Transfer width for the source in the SRC_WIDTH field.
– ii. Transfer width for the destination in the DST_WIDTH field.
– iii. Source AHB master interface layer in the SIF field where source resides.
– iv. Destination AHB master interface layer in the DIF field where destination resides.
– v. Incrementing/decrementing or fixed address for source in SRC_INCR field.
– vi. Incrementing/decrementing or fixed address for destination DST_INCR field.
Channel Disabled by
nation) and flow control peripheral by programming the FC of the DMAC_CTRLBx
register.
hardware
Buffer Complete interrupt
generated here
yes
Stall until STALLED is cleared
DADDRx, CTRLAx, CTRLBx
by writing to KEEPON field
Replay mode for SADDRx,
HDMA State Machine table?
Channel Enabled by
Is HDMA in Row1 of
EBCIMR[x]=1?
Buffer Transfer
software
yes
no
no
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