AT91SAM9G45-CU-999 Atmel, AT91SAM9G45-CU-999 Datasheet - Page 1109
AT91SAM9G45-CU-999
Manufacturer Part Number
AT91SAM9G45-CU-999
Description
IC MCU ARM9 APMC 324TFBGA
Manufacturer
Atmel
Series
AT91SAMr
Datasheet
1.AT91SAM9G45-EKES.pdf
(1218 pages)
Specifications of AT91SAM9G45-CU-999
Core Processor
ARM9
Core Size
16/32-Bit
Speed
400MHz
Connectivity
EBI/EMI, Ethernet, I²C, IrDA, MMC, SPI, SSC, UART/USART, USB
Peripherals
AC'97, DMA, I²S, LCD, POR, PWM, WDT
Number Of I /o
160
Program Memory Size
64KB (64K x 8)
Program Memory Type
ROM
Ram Size
128K x 8
Voltage - Supply (vcc/vdd)
0.9 V ~ 1.1 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
324-TFBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Supplier Unconfirmed
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Manufacturer
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Figure 45-4. Full Frame Timing, MMODE=0
6438F–ATARM–21-Jun-10
The LCDDOTCK signal is used to clock the data into the LCD drivers' shift register. The data is
sent through LCDD[23:0] synchronized by default with LCDDOTCK falling edge (rising edge can
be selected). The CLKVAL field of LCDCON1 register controls the rate of this signal. The divisor
can also be bypassed with the BYPASS bit in the LCDCON1 register. In this case, the rate of
LCDDOTCK is equal to the frequency of the LCDC Core clock. The minimum period of the LCD-
DOTCK signal depends on the configuration. This information can be found in
The LCDDOTCK signal has two different timings that are selected with the CLKMOD field of the
LCDCON2 register:
Table 45-14. Minimum LCDDOTCK Period in LCDC Core Clock Cycles
The LCDDEN signal indicates valid data in the LCD Interface.
After each horizontal line of data has been shifted into the LCD, the LCDHSYNC is asserted to
cause the line to be displayed on the panel.
The following timing parameters can be configured:
DISTYPE
TFT
STN Mono
STN Mono
STN Mono
STN Mono
STN Color
STN Color
STN Color
STN Color
• Always Active (used with TFT LCD Modules)
• Active only when data is available (used with STN LCD Modules)
LCDDOTCK
LCDMOD
LCDVSYNC
f
LCDDOTCK
Line1
Line2
Line3
SCAN
Single
Single
Dual
Dual
Single
Single
Dual
Dual
=
Line4
------------------------------- -
CLKVAL
Configuration
f
LCDC_clock
Line5
+
1
IFWIDTH
4
8
8
16
4
8
8
16
AT91SAM9G45
LCDDOTCK Period
1
4
8
8
16
2
2
4
6
Table
45-14.
1109
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