AT91SAM9G45-CU-999 Atmel, AT91SAM9G45-CU-999 Datasheet - Page 1058
AT91SAM9G45-CU-999
Manufacturer Part Number
AT91SAM9G45-CU-999
Description
IC MCU ARM9 APMC 324TFBGA
Manufacturer
Atmel
Series
AT91SAMr
Datasheet
1.AT91SAM9G45-EKES.pdf
(1218 pages)
Specifications of AT91SAM9G45-CU-999
Core Processor
ARM9
Core Size
16/32-Bit
Speed
400MHz
Connectivity
EBI/EMI, Ethernet, I²C, IrDA, MMC, SPI, SSC, UART/USART, USB
Peripherals
AC'97, DMA, I²S, LCD, POR, PWM, WDT
Number Of I /o
160
Program Memory Size
64KB (64K x 8)
Program Memory Type
ROM
Ram Size
128K x 8
Voltage - Supply (vcc/vdd)
0.9 V ~ 1.1 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
324-TFBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Supplier Unconfirmed
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43.7.3.1
43.7.3.2
1058
AT91SAM9G45
AC97 Controller Setup
Transmit Operation
The following operations must be performed in order to bring the AC97 Controller into an operat-
ing state:
The application must perform the following steps in order to send data via a channel to the AC97
Codec:
Once data has been transferred to the Channel x Shift Register, the TXRDY flag is automatically
set by the AC97 Controller which allows the application to start a new write action. The applica-
tion can also wait for an interrupt notice associated with TXRDY in order to send data. The
interrupt remains active until TXRDY flag is cleared.
1. Enable the AC97 Controller clock in the PMC controller.
2. Turn on AC97 function by enabling the ENA bit in AC97 Controller Mode Register
3. Configure the input channel assignment by controlling the AC97 Controller Input
4. Configure the output channel assignment by controlling the AC97 Controller Input
5. Configure sample width for Channel A, Channel Bby writing the SIZE bit field in AC97C
6. Configure data Endianness for Channel A, Channel B by writing CEM bit field in
7. Configure the PIO controller to drive the RESET signal of the external Codec. The
8. Enable Channel A and/or Channel B by writing CEN bit field in AC97C_CxMR register.
• Check if previous data has been sent by polling TXRDY flag in the AC97C Channel x Status
• Write data to the AC97 Controller Channel x Transmit Holding Register (AC97C_CxTHR).
Register (AC97_CxSR). x being one of the 2 channels.
(AC97C_MR).
Assignment Register (AC97C_ICA).
Assignment Register (AC97C_OCA).
Channel x Mode Register (AC97C_CAMR), (AC97C_CBMR). The application can write
10, 16, 18,or 20-bit wide PCM samples through the AC97 interface and they will be
transferred into 20-bit wide slots.
(AC97C_CAMR), (AC97C_CBMR) register. Data on the AC-link are shifted MSB first.
The application can write little- or big-endian data to the AC97 Controller interface.
RESET signal must fulfill external AC97 Codec timing requirements.
6438F–ATARM–21-Jun-10
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