LPC1759FBD80,551 NXP Semiconductors, LPC1759FBD80,551 Datasheet - Page 151

• Manufacturer Part Number: LPC1759FBD80,551
• Description: IC ARM CORTEX MCU 512K 80-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC17xxr

Specifications of LPC1759FBD80,551

• Program Memory Type: FLASH
• Program Memory Size: 512KB (512K x 8)
• Package / Case: 80-LQFP
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 120MHz
• Connectivity: CAN, I²C, IrDA, Microwire, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 52
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 6x12b, D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC17
• Core: ARM Cortex M3
• Data Bus Width: 32 bit
• Data Ram Size: 64 KB
• Interface Type: Ethernet, USB, OTG, CAN
• Maximum Clock Frequency: 120 MHz
• Number Of Programmable I/os: 52
• Number Of Timers: 4
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 6 Channel
• On-chip Dac: 10 bit
• Package: 80LQFP
• Device Core: ARM Cortex M3
• Family Name: LPC17xx
• Maximum Speed: 120 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4968; 935290523551

NXP Semiconductors
Table 130. MAC Configuration register 2 (MAC2 - address 0x5000 0004) bit description
UM10360
User manual
Bit
0
1
2
3
4
5
6
7
8
9
11:10
12
13
14
31:15
Symbol
FULL-DUPLEX
FRAME LENGTH
CHECKING
HUGE FRAME
ENABLE
DELAYED CRC
CRC ENABLE
PAD / CRC ENABLE
VLAN PAD ENABLE
AUTO DETECT PAD
ENABLE
PURE PREAMBLE
ENFORCEMENT
LONG PREAMBLE
ENFORCEMENT
-
NO BACKOFF
BACK PRESSURE /
NO BACKOFF
EXCESS DEFER
-
Set this bit to cause the MAC to pad all short frames to 64 bytes and append a valid
When enabled (set to ’1’) the MAC will defer to carrier indefinitely as per the
Function
When enabled (set to ’1’), the MAC operates in Full-Duplex mode. When disabled,
the MAC operates in Half-Duplex mode.
When enabled (set to ’1’), both transmit and receive frame lengths are compared to
the Length/Type field. If the Length/Type field represents a length then the check is
performed. Mismatches are reported in the StatusInfo word for each received frame.
When enabled (set to ’1’), frames of any length are transmitted and received.
This bit determines the number of bytes, if any, of proprietary header information
that exist on the front of IEEE 802.3 frames. When 1, four bytes of header (ignored
by the CRC function) are added. When 0, there is no proprietary header.
Set this bit to append a CRC to every frame whether padding was required or not.
Must be set if PAD/CRC ENABLE is set. Clear this bit if frames presented to the
MAC contain a CRC.
Set this bit to have the MAC pad all short frames. Clear this bit if frames presented
to the MAC have a valid length. This bit is used in conjunction with AUTO PAD
ENABLE and VLAN PAD ENABLE. See
pad function.
CRC. Consult
padding features.
Note: This bit is ignored if PAD / CRC ENABLE is cleared.
Set this bit to cause the MAC to automatically detect the type of frame, either tagged
or un-tagged, by comparing the two octets following the source address with
0x8100 (VLAN Protocol ID) and pad accordingly.
provides a description of the pad function based on the configuration of this register.
Note: This bit is ignored if PAD / CRC ENABLE is cleared.
When enabled (set to ’1’), the MAC will verify the content of the preamble to ensure
it contains 0x55 and is error-free. A packet with an incorrect preamble is discarded.
When disabled, no preamble checking is performed.
When enabled (set to ’1’), the MAC only allows receive packets which contain
preamble fields less than 12 bytes in length. When disabled, the MAC allows any
length preamble as per the Standard.
Reserved. User software should not write ones to reserved bits. The value read
from a reserved bit is not defined.
When enabled (set to ’1’), the MAC will immediately retransmit following a collision
rather than using the Binary Exponential Backoff algorithm as specified in the
Standard.
When enabled (set to ’1’), after the MAC incidentally causes a collision during back
pressure, it will immediately retransmit without backoff, reducing the chance of
further collisions and ensuring transmit packets get sent.
Standard. When disabled, the MAC will abort when the excessive deferral limit is
reached.
Reserved. User software should not write ones to reserved bits. The value read
from a reserved bit is not defined.
All information provided in this document is subject to legal disclaimers.
Table 132
Rev. 2 — 19 August 2010
- Pad Operation for more information on the various
Table 132
Table 132
- Pad Operation for details on the
Chapter 10: LPC17xx Ethernet
- Pad Operation
UM10360
© NXP B.V. 2010. All rights reserved.
151 of 840
Reset
value
0
0
0
0
0
0
0
0
0
0
0x0
0
0
0
0x0