LPC1759FBD80,551 NXP Semiconductors, LPC1759FBD80,551 Datasheet - Page 777

• Manufacturer Part Number: LPC1759FBD80,551
• Description: IC ARM CORTEX MCU 512K 80-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC17xxr

Specifications of LPC1759FBD80,551

• Program Memory Type: FLASH
• Program Memory Size: 512KB (512K x 8)
• Package / Case: 80-LQFP
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 120MHz
• Connectivity: CAN, I²C, IrDA, Microwire, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 52
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 6x12b, D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC17
• Core: ARM Cortex M3
• Data Bus Width: 32 bit
• Data Ram Size: 64 KB
• Interface Type: Ethernet, USB, OTG, CAN
• Maximum Clock Frequency: 120 MHz
• Number Of Programmable I/os: 52
• Number Of Timers: 4
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 6 Channel
• On-chip Dac: 10 bit
• Package: 80LQFP
• Device Core: ARM Cortex M3
• Family Name: LPC17xx
• Maximum Speed: 120 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4968; 935290523551

NXP Semiconductors
UM10360
User manual
34.4.3.11.1 Memory Management Fault Status Register
34.4.3.11 Configurable Fault Status Register
The CFSR indicates the cause of a memory management fault, bus fault, or usage fault.
See the register summary in
The following subsections describe the subregisters that make up the CFSR:
The CFSR is byte accessible. You can access the CFSR or its subregisters as follows:
The flags in the MMFSR indicate the cause of memory access faults. The bit assignments
are shown in
Table 668. MMFSR bit assignments
Bits
[7]
[6:5]
[4]
•
•
•
•
•
•
•
•
Table 668 “MMFSR bit assignments”
Table 673 “BFAR bit assignments”
Table 670 “UFSR bit
access the complete CFSR with a word access to 0xE000ED28
access the MMFSR with a byte access to 0xE000ED28
access the MMFSR and BFSR with a halfword access to 0xE000ED28
access the BFSR with a byte access to 0xE000ED29
access the UFSR with a halfword access to 0xE000ED2A.
31
Name
MMARVALID
-
MSTKERR
Table
All information provided in this document is subject to legal disclaimers.
Usage Fault Status Register
668.
Rev. 2 — 19 August 2010
UFSR
assignments”.
Function
Memory Management Fault Address Register (MMAR) valid flag:
0 = value in MMAR is not a valid fault address
1 = MMAR holds a valid fault address.
If a memory management fault occurs and is escalated to a hard
fault because of priority, the hard fault handler must set this bit to 0.
This prevents problems on return to a stacked active memory
management fault handler whose MMAR value has been
overwritten.
Reserved.
Memory manager fault on stacking for exception entry:
0 = no stacking fault
1 = stacking for an exception entry has caused one or more access
violations.
When this bit is 1, the SP is still adjusted but the values in the
context area on the stack might be incorrect. The processor has not
written a fault address to the MMAR.
Table 654
for its attributes. The bit assignments are:
Chapter 34: Appendix: Cortex-M3 user guide
16 15
Bus Fault Status
Register
BFSR
8 7
UM10360
Memory Management
Fault Status Register
© NXP B.V. 2010. All rights reserved.
MMFSR
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