LPC1759FBD80,551 NXP Semiconductors, LPC1759FBD80,551 Datasheet - Page 678

• Manufacturer Part Number: LPC1759FBD80,551
• Description: IC ARM CORTEX MCU 512K 80-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC17xxr

Specifications of LPC1759FBD80,551

• Program Memory Type: FLASH
• Program Memory Size: 512KB (512K x 8)
• Package / Case: 80-LQFP
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 120MHz
• Connectivity: CAN, I²C, IrDA, Microwire, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 52
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 6x12b, D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC17
• Core: ARM Cortex M3
• Data Bus Width: 32 bit
• Data Ram Size: 64 KB
• Interface Type: Ethernet, USB, OTG, CAN
• Maximum Clock Frequency: 120 MHz
• Number Of Programmable I/os: 52
• Number Of Timers: 4
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 6 Channel
• On-chip Dac: 10 bit
• Package: 80LQFP
• Device Core: ARM Cortex M3
• Family Name: LPC17xx
• Maximum Speed: 120 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4968; 935290523551

NXP Semiconductors
UM10360
User manual
34.2.5.1.1 Syntax
34.2.5.1.2 Operation
34.2.5.1.3 Restrictions
34.2.5.1 ADD, ADC, SUB, SBC, and RSB
Add, Add with carry, Subtract, Subtract with carry, and Reverse Subtract.
op{S}{cond} {Rd,} Rn, Operand2
op{cond} {Rd,} Rn, #imm12
where:
op is one of:
S: is an optional suffix. If S is specified, the condition code flags are updated on the result
of the operation, see
cond: is an optional condition code, see
Rd is the destination register. If Rd is omitted, the destination register is Rn.
Rn is the register holding the first operand.
Operand2 is a flexible second operand. See
imm12 is any value in the range 0-4095.
The ADD instruction adds the value of Operand2 or imm12 to the value in Rn.
The ADC instruction adds the values in Rn and Operand2, together with the carry flag.
The SUB instruction subtracts the value of Operand2 or imm12 from the value in Rn.
The SBC instruction subtracts the value of Operand2 from the value in Rn. If the carry flag
is clear, the result is reduced by one.
The RSB instruction subtracts the value in Rn from the value of Operand2. This is useful
because of the wide range of options for Operand2.
Use ADC and SBC to synthesize multiword arithmetic, see
See also
Remark: ADDW is equivalent to the ADD syntax that uses the imm12 operand. SUBW is
equivalent to the SUB syntax that uses the imm12 operand.
•
•
ADD: Add.
ADC: Add with Carry.
SUB: Subtract.
RSB: Reverse Subtract.
Operand2 must not be SP and must not be PC
Rd can be SP only in ADD and SUB, and only with the additional restrictions:
Section
All information provided in this document is subject to legal disclaimers.
34.2.4.1.
Section 34.2.3.7 “Conditional
Rev. 2 — 19 August 2010
; ADD and SUB only
Section 34.2.3.7 “Conditional
Chapter 34: Appendix: Cortex-M3 user guide
Section 34.2.3.3
execution”.
Section
for details of the options.
34.2.5.1.6.
UM10360
execution”.
© NXP B.V. 2010. All rights reserved.
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