LPC1759FBD80,551 NXP Semiconductors, LPC1759FBD80,551 Datasheet - Page 793

• Manufacturer Part Number: LPC1759FBD80,551
• Description: IC ARM CORTEX MCU 512K 80-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC17xxr

Specifications of LPC1759FBD80,551

• Program Memory Type: FLASH
• Program Memory Size: 512KB (512K x 8)
• Package / Case: 80-LQFP
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 120MHz
• Connectivity: CAN, I²C, IrDA, Microwire, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 52
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 6x12b, D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC17
• Core: ARM Cortex M3
• Data Bus Width: 32 bit
• Data Ram Size: 64 KB
• Interface Type: Ethernet, USB, OTG, CAN
• Maximum Clock Frequency: 120 MHz
• Number Of Programmable I/os: 52
• Number Of Timers: 4
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 6 Channel
• On-chip Dac: 10 bit
• Package: 80LQFP
• Device Core: ARM Cortex M3
• Family Name: LPC17xx
• Maximum Speed: 120 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4968; 935290523551

NXP Semiconductors
UM10360
User manual
34.4.5.8.1 Updating an MPU region using separate words
34.4.5.7 MPU mismatch
34.4.5.8 Updating an MPU region
Table 689. AP encoding
When an access violates the MPU permissions, the processor generates a memory
management fault, see
indicates the cause of the fault. See
To update the attributes for an MPU region, update the RNR, RBAR and RASR registers.
You can program each register separately, or use a multiple-word write to program all of
these registers. You can use the RBAR and RASR aliases to program up to four regions
simultaneously using an STM instruction.
Simple code to configure one region:
; R1 = region number
; R2 = size/enable
; R3 = attributes
; R4 = address
LDR R0,=MPU_RNR
STR R1, [R0, #0x0]
STR R4, [R0, #0x4]
STRH R2, [R0, #0x8]
STRH R3, [R0, #0xA]
Disable a region before writing new region settings to the MPU if you have previously
enabled the region being changed. For example:
; R1 = region number
; R2 = size/enable
AP[2:0]
000
001
010
011
100
101
110
111
Privileged
permissions
No access
RW
RW
RW
Unpredictable Unpredictable
RO
RO
RO
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 19 August 2010
Section 34.3.1.4 “Exceptions and
; 0xE000ED98, MPU region number register
; Region Number
; Region Base Address
; Region Size and Enable
; Region Attribute
Unprivileged
permissions
No access
RO
RW
No access
RO
RO
No access
Table 668
Chapter 34: Appendix: Cortex-M3 user guide
Description
All accesses generate a permission fault
Access from privileged software only
Writes by unprivileged software generate a
permission fault
Full access
Reserved
Reads by privileged software only
Read only, by privileged or unprivileged software
Read only, by privileged or unprivileged software
for more information.
interrupts”. The MMFSR
UM10360
© NXP B.V. 2010. All rights reserved.
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