LPC1759FBD80,551 NXP Semiconductors, LPC1759FBD80,551 Datasheet - Page 706

• Manufacturer Part Number: LPC1759FBD80,551
• Description: IC ARM CORTEX MCU 512K 80-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC17xxr

Specifications of LPC1759FBD80,551

• Program Memory Type: FLASH
• Program Memory Size: 512KB (512K x 8)
• Package / Case: 80-LQFP
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 120MHz
• Connectivity: CAN, I²C, IrDA, Microwire, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 52
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 6x12b, D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC17
• Core: ARM Cortex M3
• Data Bus Width: 32 bit
• Data Ram Size: 64 KB
• Interface Type: Ethernet, USB, OTG, CAN
• Maximum Clock Frequency: 120 MHz
• Number Of Programmable I/os: 52
• Number Of Timers: 4
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 6 Channel
• On-chip Dac: 10 bit
• Package: 80LQFP
• Device Core: ARM Cortex M3
• Family Name: LPC17xx
• Maximum Speed: 120 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4968; 935290523551

NXP Semiconductors
UM10360
User manual
34.2.9.1.1 Syntax
34.2.9.1.2 Operation
34.2.9.1 B, BL, BX, and BLX
Branch instructions.
B{cond} label
BL{cond} label
BX{cond} Rm
BLX{cond} Rm
where:
B is branch (immediate).
BL is branch with link (immediate).
BX is branch indirect (register).
BLX is branch indirect with link (register).
cond is an optional condition code, see
label is a PC-relative expression. See
Rm is a register that indicates an address to branch to. Bit[0] of the value in Rm must be
1, but the address to branch to is created by changing bit[0] to 0.
All these instructions cause a branch to label, or to the address indicated in Rm. In
addition:
Bcond label is the only conditional instruction that can be either inside or outside an IT
block. All other branch instructions must be conditional inside an IT block, and must be
unconditional outside the IT block, see
Table 623
Table 623. Branch ranges
Remark: You might have to use the .W suffix to get the maximum branch range. See
Section 34.2.3.8 “Instruction width
Instruction
B label
Bcond label (outside IT block)
Bcond label (inside IT block)
BL { cond } label
BX { cond } Rm
BLX { cond } Rm
•
•
The BL and BLX instructions write the address of the next instruction to LR (the link
register, R14).
The BX and BLX instructions cause a UsageFault exception if bit[0] of Rm is 0.
shows the ranges for the various branch instructions.
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 19 August 2010
selection”.
Section 34.2.3.6 “PC-relative
Section
Section 34.2.3.7 “Conditional
Chapter 34: Appendix: Cortex-M3 user guide
Branch range
− 16 MB to +16 MB
− 1 MB to +1 MB
− 16 MB to +16 MB
− 16 MB to +16 MB
Any value in register
Any value in register
34.2.9.3.
expressions”.
execution”.
UM10360
© NXP B.V. 2010. All rights reserved.
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