LPC1759FBD80,551 NXP Semiconductors, LPC1759FBD80,551 Datasheet - Page 613

• Manufacturer Part Number: LPC1759FBD80,551
• Description: IC ARM CORTEX MCU 512K 80-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC17xxr

Specifications of LPC1759FBD80,551

• Program Memory Type: FLASH
• Program Memory Size: 512KB (512K x 8)
• Package / Case: 80-LQFP
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 120MHz
• Connectivity: CAN, I²C, IrDA, Microwire, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 52
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 6x12b, D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC17
• Core: ARM Cortex M3
• Data Bus Width: 32 bit
• Data Ram Size: 64 KB
• Interface Type: Ethernet, USB, OTG, CAN
• Maximum Clock Frequency: 120 MHz
• Number Of Programmable I/os: 52
• Number Of Timers: 4
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 6 Channel
• On-chip Dac: 10 bit
• Package: 80LQFP
• Device Core: ARM Cortex M3
• Family Name: LPC17xx
• Maximum Speed: 120 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4968; 935290523551

NXP Semiconductors
UM10360
User manual
Fig 135. LLI example
0x2002 0000
0x2002 0010
0x2002 0020
0x2002 0070
LLI1
LLI2
LLI3
LLI8
Source address
Destination address = peripheral
Next LLI address
Control information
Source address
Destination address = peripheral
Next LLI address
Control information
Source address
Destination address = peripheral
Next LLI address
Control information
Source address
Destination address = peripheral
Next LLI address
Control information
The first LLI, stored at 0x2002 0000, defines the first block of data to be transferred, which
is the data stored from address 0x2002 A200 to 0x2002 ADFF:
The second LLI, stored at 0x2002 0010, describes the next block of data to be transferred:
A chain of descriptors is built up, each one pointing to the next in the series. To initialize
the DMA stream, the first LLI, 0x2002 0000, is programmed into the DMA Controller.
When the first packet of data has been transferred the next LLI is automatically loaded.
The final LLI is stored at 0x2002 0070 and contains:
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•
•
•
•
•
•
•
•
•
•
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Source start address 0x2002 A200.
Destination address set to the destination peripheral address.
Transfer width, word (32-bit).
Transfer size, 3072 bytes (0XC00).
Source and destination burst sizes, 16 transfers.
Next LLI address, 0x2002 0010.
Source start address 0x2002 B200.
Destination address set to the destination peripheral address.
Transfer width, word (32-bit).
Transfer size, 3072 bytes (0xC00).
Source and destination burst sizes, 16 transfers.
Next LLI address, 0x2002 0020.
Linked List Array
All information provided in this document is subject to legal disclaimers.
= 0x 2002 A200
= 0x2002 0010
= length 3072
= 0x 2002 B200
= 0x2002 0020
= length 3072
= 0x 2002 C200
= 0x2002 0030
= length 3072
= 0x 2003 1200
= 0 (end of list)
= length 3072
Rev. 2 — 19 August 2010
Chapter 31: LPC17xx General Purpose DMA (GPDMA)
0x2002 ADFF
0x2002 BDFF
0x2002 CDFF
0x2003 1DFF
0x2002 C200
0x2002 A200
0x2002 B200
0x2003 1200
3072 bytes of data
3072 bytes of data
3072 bytes of data
3072 bytes of data
UM10360
© NXP B.V. 2010. All rights reserved.
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