LPC1759FBD80,551 NXP Semiconductors, LPC1759FBD80,551 Datasheet - Page 823

• Manufacturer Part Number: LPC1759FBD80,551
• Description: IC ARM CORTEX MCU 512K 80-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC17xxr

Specifications of LPC1759FBD80,551

• Program Memory Type: FLASH
• Program Memory Size: 512KB (512K x 8)
• Package / Case: 80-LQFP
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 120MHz
• Connectivity: CAN, I²C, IrDA, Microwire, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 52
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 6x12b, D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC17
• Core: ARM Cortex M3
• Data Bus Width: 32 bit
• Data Ram Size: 64 KB
• Interface Type: Ethernet, USB, OTG, CAN
• Maximum Clock Frequency: 120 MHz
• Number Of Programmable I/os: 52
• Number Of Timers: 4
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 6 Channel
• On-chip Dac: 10 bit
• Package: 80LQFP
• Device Core: ARM Cortex M3
• Family Name: LPC17xx
• Maximum Speed: 120 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4968; 935290523551

NXP Semiconductors
11.12
11.12.1
11.12.2
11.12.3
11.12.4
11.12.5
11.12.6
11.12.7
11.12.8
11.12.9
11.12.10 Select Endpoint (Command: 0x00 - 0x1F, Data:
11.12.11 Select Endpoint/Clear Interrupt (Command:
11.12.12 Set Endpoint Status (Command: 0x40 - 0x55,
11.12.13 Clear Buffer (Command: 0xF2, Data: read 1 byte
11.12.14 Validate Buffer (Command: 0xFA, Data: none). . .
11.13
11.14
11.14.1
11.14.2
11.14.3
11.15
11.15.1
11.15.2
11.15.3
11.15.4
11.15.4.1 Next_DD_pointer . . . . . . . . . . . . . . . . . . . . . 257
11.15.4.2 DMA_mode. . . . . . . . . . . . . . . . . . . . . . . . . . 258
11.15.4.3 Next_DD_valid . . . . . . . . . . . . . . . . . . . . . . . 258
Chapter 12: LPC17xx USB Host controller
12.1
12.2
12.3
12.3.1
UM10360
User manual
Serial interface engine command description
USB device controller initialization . . . . . . . 252
Slave mode operation . . . . . . . . . . . . . . . . . . 253
DMA operation . . . . . . . . . . . . . . . . . . . . . . . . 254
How to read this chapter . . . . . . . . . . . . . . . . 269
Basic configuration . . . . . . . . . . . . . . . . . . . . 269
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . 269
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244
Set Address (Command: 0xD0, Data: write 1
byte) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245
Configure Device (Command: 0xD8, Data: write
1 byte). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245
Set Mode (Command: 0xF3, Data: write
1 byte). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246
Read Current Frame Number (Command: 0xF5,
Data: read 1 or 2 bytes) . . . . . . . . . . . . . . . . 246
Read Test Register (Command: 0xFD, Data: read
2 bytes) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247
Set Device Status (Command: 0xFE, Data: write 1
byte) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247
Get Device Status (Command: 0xFE, Data: read 1
byte) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248
Get Error Code (Command: 0xFF, Data: read 1
byte) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248
Read Error Status (Command: 0xFB, Data: read 1
byte) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249
read 1 byte (optional)) . . . . . . . . . . . . . . . . . 249
0x40 - 0x5F, Data: read 1 byte) . . . . . . . . . . 250
Data: write 1 byte (optional)). . . . . . . . . . . . . 251
(optional)) . . . . . . . . . . . . . . . . . . . . . . . . . . . 251
252
Interrupt generation . . . . . . . . . . . . . . . . . . . 253
Data transfer for OUT endpoints. . . . . . . . . . 254
Data transfer for IN endpoints. . . . . . . . . . . . 254
Transfer terminology. . . . . . . . . . . . . . . . . . . 255
USB device communication area . . . . . . . . . 255
Triggering the DMA engine. . . . . . . . . . . . . . 256
The DMA descriptor . . . . . . . . . . . . . . . . . . . 256
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . 270
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 19 August 2010
11.15.4.4 Isochronous_endpoint . . . . . . . . . . . . . . . . . 258
11.15.4.5 Max_packet_size . . . . . . . . . . . . . . . . . . . . . 258
11.15.4.6 DMA_buffer_length . . . . . . . . . . . . . . . . . . . 258
11.15.4.7 DMA_buffer_start_addr . . . . . . . . . . . . . . . . 258
11.15.4.8 DD_retired . . . . . . . . . . . . . . . . . . . . . . . . . . 258
11.15.4.9 DD_status . . . . . . . . . . . . . . . . . . . . . . . . . . 258
11.15.4.10 Packet_valid . . . . . . . . . . . . . . . . . . . . . . . . 259
11.15.4.11 LS_byte_extracted . . . . . . . . . . . . . . . . . . . 259
11.15.4.12 MS_byte_extracted . . . . . . . . . . . . . . . . . . . 259
11.15.4.13 Present_DMA_count . . . . . . . . . . . . . . . . . . 259
11.15.4.14 Message_length_position . . . . . . . . . . . . . . 259
11.15.4.15 Isochronous_packetsize_memory_address 259
11.15.5
11.15.5.1 Setting up DMA transfers. . . . . . . . . . . . . . . 260
11.15.5.2 Finding DMA Descriptor. . . . . . . . . . . . . . . . 260
11.15.5.3 Transferring the data . . . . . . . . . . . . . . . . . . 260
11.15.5.4 Optimizing descriptor fetch . . . . . . . . . . . . . 260
11.15.5.5 Ending the packet transfer . . . . . . . . . . . . . . 261
11.15.5.6 No_Packet DD . . . . . . . . . . . . . . . . . . . . . . . 261
11.15.6
11.15.6.1 Setting up DMA transfers. . . . . . . . . . . . . . . 261
11.15.6.2 Finding the DMA Descriptor. . . . . . . . . . . . . 262
11.15.6.3 Transferring the Data . . . . . . . . . . . . . . . . . . 262
11.15.6.4 DMA descriptor completion . . . . . . . . . . . . . 262
11.15.6.5 Isochronous OUT Endpoint Operation
11.15.7
11.15.7.1 Setting up the DMA transfer. . . . . . . . . . . . . 265
11.15.7.2 Finding the DMA Descriptor. . . . . . . . . . . . . 265
11.15.7.3 Transferring the Data . . . . . . . . . . . . . . . . . . 265
11.15.7.4 Ending the packet transfer . . . . . . . . . . . . . . 266
11.16
11.16.1
11.16.2
12.3.2
12.4
12.4.1
12.4.1.1
Double buffered endpoint operation . . . . . . 266
Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . 270
Non-isochronous endpoint operation . . . . . . 260
Isochronous endpoint operation. . . . . . . . . . 261
OUT endpoints. . . . . . . . . . . . . . . . . . . . . . . . 262
IN endpoints. . . . . . . . . . . . . . . . . . . . . . . . . . 262
Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262
Auto Length Transfer Extraction (ATLE) mode
operation . . . . . . . . . . . . . . . . . . . . . . . . . . . 263
OUT transfers in ATLE mode. . . . . . . . . . . . . 263
IN transfers in ATLE mode. . . . . . . . . . . . . . . 265
OUT endpoints. . . . . . . . . . . . . . . . . . . . . . . . 265
IN endpoints. . . . . . . . . . . . . . . . . . . . . . . . . . 265
OUT endpoints. . . . . . . . . . . . . . . . . . . . . . . . 266
IN endpoints. . . . . . . . . . . . . . . . . . . . . . . . . . 266
Bulk endpoints . . . . . . . . . . . . . . . . . . . . . . . 266
Isochronous endpoints . . . . . . . . . . . . . . . . . 268
Architecture . . . . . . . . . . . . . . . . . . . . . . . . . 270
Pin description . . . . . . . . . . . . . . . . . . . . . . . 271
USB host usage note . . . . . . . . . . . . . . . . . . 271
Chapter 35: Supplementary information
UM10360
© NXP B.V. 2010. All rights reserved.
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